* [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-16 10:24 ` Igor Mammedov
2024-07-15 17:11 ` [PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART Sunil V L
` (7 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
(BRS) specification [1], PLIC and APLIC should be in namespace as well.
So, add them using the defined HID.
[1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
(commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 0925528160..5f5082a35b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
+static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
+ uint64_t mmio_base, uint64_t mmio_size,
+ const char *hid)
+{
+ uint64_t plic_aplic_addr;
+ uint32_t gsi_base;
+ uint8_t socket;
+
+ for (socket = 0; socket < socket_count; socket++) {
+ plic_aplic_addr = mmio_base + mmio_size * socket;
+ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ Aml *dev = aml_device("IC%.02X", socket);
+ aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+ aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
+ AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ }
+}
+
static void
acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
uint32_t uart_irq)
@@ -411,6 +435,14 @@ static void build_dsdt(GArray *table_data,
socket_count = riscv_socket_count(ms);
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
+ memmap[VIRT_PLIC].size, "RSCV0001");
+ } else {
+ acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
+ memmap[VIRT_APLIC_S].size, "RSCV0002");
+ }
+
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
if (socket_count == 1) {
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
2024-07-15 17:11 ` [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC Sunil V L
@ 2024-07-16 10:24 ` Igor Mammedov
2024-07-16 12:14 ` Sunil V L
0 siblings, 1 reply; 14+ messages in thread
From: Igor Mammedov @ 2024-07-16 10:24 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Michael S . Tsirkin, Ani Sinha
On Mon, 15 Jul 2024 22:41:21 +0530
Sunil V L <sunilvl@ventanamicro.com> wrote:
> As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
> (BRS) specification [1], PLIC and APLIC should be in namespace as well.
> So, add them using the defined HID.
>
> [1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
> (commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)
in spec links 'See RVI ACPI IDs' and right below it 'additional guidance',
do lead nowhere hence do not clarify anything.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 0925528160..5f5082a35b 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> }
> }
>
> +static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
> + uint64_t mmio_base, uint64_t mmio_size,
> + const char *hid)
> +{
> + uint64_t plic_aplic_addr;
> + uint32_t gsi_base;
> + uint8_t socket;
> +
> + for (socket = 0; socket < socket_count; socket++) {
> + plic_aplic_addr = mmio_base + mmio_size * socket;
> + gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> + Aml *dev = aml_device("IC%.02X", socket);
> + aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
> + aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
> + aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
> + AML_READ_WRITE));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + }
> +}
> +
> static void
> acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> uint32_t uart_irq)
> @@ -411,6 +435,14 @@ static void build_dsdt(GArray *table_data,
>
> socket_count = riscv_socket_count(ms);
>
> + if (s->aia_type == VIRT_AIA_TYPE_NONE) {
> + acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
> + memmap[VIRT_PLIC].size, "RSCV0001");
> + } else {
> + acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
> + memmap[VIRT_APLIC_S].size, "RSCV0002");
> + }
> +
> acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
>
> if (socket_count == 1) {
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
2024-07-16 10:24 ` Igor Mammedov
@ 2024-07-16 12:14 ` Sunil V L
0 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-16 12:14 UTC (permalink / raw)
To: Igor Mammedov
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Michael S . Tsirkin, Ani Sinha
On Tue, Jul 16, 2024 at 12:24:05PM +0200, Igor Mammedov wrote:
> On Mon, 15 Jul 2024 22:41:21 +0530
> Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> > As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
> > (BRS) specification [1], PLIC and APLIC should be in namespace as well.
> > So, add them using the defined HID.
> >
> > [1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
> > (commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)
>
> in spec links 'See RVI ACPI IDs' and right below it 'additional guidance',
> do lead nowhere hence do not clarify anything.
>
Thanks Igor. I didn't realize links work only in the final PDF generated
from the sources. Let me point to the PDF itself where these
requirements were documented first.
Thanks,
Sunil
> >
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Alistair Francis <alistair.francis@wdc.com>
>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
>
> > ---
> > hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> >
> > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> > index 0925528160..5f5082a35b 100644
> > --- a/hw/riscv/virt-acpi-build.c
> > +++ b/hw/riscv/virt-acpi-build.c
> > @@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> > }
> > }
> >
> > +static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
> > + uint64_t mmio_base, uint64_t mmio_size,
> > + const char *hid)
> > +{
> > + uint64_t plic_aplic_addr;
> > + uint32_t gsi_base;
> > + uint8_t socket;
> > +
> > + for (socket = 0; socket < socket_count; socket++) {
> > + plic_aplic_addr = mmio_base + mmio_size * socket;
> > + gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> > + Aml *dev = aml_device("IC%.02X", socket);
> > + aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
> > + aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
> > +
> > + Aml *crs = aml_resource_template();
> > + aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
> > + AML_READ_WRITE));
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > + }
> > +}
> > +
> > static void
> > acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> > uint32_t uart_irq)
> > @@ -411,6 +435,14 @@ static void build_dsdt(GArray *table_data,
> >
> > socket_count = riscv_socket_count(ms);
> >
> > + if (s->aia_type == VIRT_AIA_TYPE_NONE) {
> > + acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
> > + memmap[VIRT_PLIC].size, "RSCV0001");
> > + } else {
> > + acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
> > + memmap[VIRT_APLIC_S].size, "RSCV0002");
> > + }
> > +
> > acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
> >
> > if (socket_count == 1) {
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
2024-07-15 17:11 ` [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-16 10:28 ` Igor Mammedov
2024-07-15 17:11 ` [PATCH v3 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64 Sunil V L
` (6 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
The requirement ACPI_060 in the RISC-V BRS specification [1], requires
NS16550 compatible UART to have the HID RSCV0003. So, update the HID for
the UART.
[1] - https://github.com/riscv-non-isa/riscv-brs/commits/main/acpi.adoc
(commit: 7bfa87e86ad5658283731207dbfc8ab3744d3265)
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt-acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 5f5082a35b..36d6a3a412 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -170,7 +170,7 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
uint32_t uart_irq)
{
Aml *dev = aml_device("COM0");
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+ aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003")));
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
Aml *crs = aml_resource_template();
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART
2024-07-15 17:11 ` [PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART Sunil V L
@ 2024-07-16 10:28 ` Igor Mammedov
0 siblings, 0 replies; 14+ messages in thread
From: Igor Mammedov @ 2024-07-16 10:28 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Michael S . Tsirkin, Ani Sinha
On Mon, 15 Jul 2024 22:41:22 +0530
Sunil V L <sunilvl@ventanamicro.com> wrote:
> The requirement ACPI_060 in the RISC-V BRS specification [1], requires
> NS16550 compatible UART to have the HID RSCV0003. So, update the HID for
> the UART.
>
> [1] - https://github.com/riscv-non-isa/riscv-brs/commits/main/acpi.adoc
this should point to text like in previous patch and not to commit
> (commit: 7bfa87e86ad5658283731207dbfc8ab3744d3265)
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
with above fixed:
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/riscv/virt-acpi-build.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 5f5082a35b..36d6a3a412 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -170,7 +170,7 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> uint32_t uart_irq)
> {
> Aml *dev = aml_device("COM0");
> - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
> + aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003")));
> aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>
> Aml *crs = aml_resource_template();
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
2024-07-15 17:11 ` [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC Sunil V L
2024-07-15 17:11 ` [PATCH v3 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-15 17:11 ` [PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge Sunil V L
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
so that CI tests don't fail when those ACPI tables are updated in the
next patch. This is as per the documentation in bios-tables-tests.c.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..9282ea0fb2 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,7 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/DSDT",
+"tests/data/acpi/aarch64/virt/DSDT.memhp",
+"tests/data/acpi/aarch64/virt/DSDT.topology",
+"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/aarch64/virt/DSDT.pxb",
+"tests/data/acpi/x86/microvm/DSDT.pcie",
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
` (2 preceding siblings ...)
2024-07-15 17:11 ` [PATCH v3 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64 Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-16 10:33 ` Igor Mammedov
2024-07-15 17:11 ` [PATCH v3 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm Sunil V L
` (4 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
Currently, PCI link devices (PNP0C0F) are always created within the
scope of the PCI root bridge. However, RISC-V needs these link devices
to be created outside to ensure the probing order in the OS. This
matches the example given in the ACPI specification [1] as well. Hence,
create these link devices directly under _SB instead of under the PCI
root bridge.
To keep these link device names unique for multiple PCI bridges, change
the device name from GSIx to LXXY format where XX is the PCI bus number
and Y is the INTx.
GPEX is currently used by riscv, aarch64/virt and x86/microvm machines.
So, this change will alter the DSDT for those systems.
[1] - ACPI 5.1: 6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
hw/pci-host/gpex-acpi.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index f69413ea2c..391fabb8a8 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -7,7 +7,8 @@
#include "hw/pci/pcie_host.h"
#include "hw/acpi/cxl.h"
-static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
+static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,
+ Aml *scope, uint8_t bus_num)
{
Aml *method, *crs;
int i, slot_no;
@@ -20,7 +21,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
Aml *pkg = aml_package(4);
aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
aml_append(pkg, aml_int(i));
- aml_append(pkg, aml_name("GSI%d", gsi));
+ aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi));
aml_append(pkg, aml_int(0));
aml_append(rt_pkg, pkg);
}
@@ -30,7 +31,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
/* Create GSI link device */
for (i = 0; i < PCI_NUM_PINS; i++) {
uint32_t irqs = irq + i;
- Aml *dev_gsi = aml_device("GSI%d", i);
+ Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i);
aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
crs = aml_resource_template();
@@ -45,7 +46,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
aml_append(dev_gsi, aml_name_decl("_CRS", crs));
method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
aml_append(dev_gsi, method);
- aml_append(dev, dev_gsi);
+ aml_append(scope, dev_gsi);
}
}
@@ -174,7 +175,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
}
- acpi_dsdt_add_pci_route_table(dev, cfg->irq);
+ acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num);
/*
* Resources defined for PXBs are composed of the following parts:
@@ -205,7 +206,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
- acpi_dsdt_add_pci_route_table(dev, cfg->irq);
+ acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0);
method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge
2024-07-15 17:11 ` [PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge Sunil V L
@ 2024-07-16 10:33 ` Igor Mammedov
0 siblings, 0 replies; 14+ messages in thread
From: Igor Mammedov @ 2024-07-16 10:33 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Michael S . Tsirkin, Ani Sinha
On Mon, 15 Jul 2024 22:41:24 +0530
Sunil V L <sunilvl@ventanamicro.com> wrote:
> Currently, PCI link devices (PNP0C0F) are always created within the
> scope of the PCI root bridge. However, RISC-V needs these link devices
> to be created outside to ensure the probing order in the OS. This
> matches the example given in the ACPI specification [1] as well. Hence,
> create these link devices directly under _SB instead of under the PCI
> root bridge.
>
> To keep these link device names unique for multiple PCI bridges, change
> the device name from GSIx to LXXY format where XX is the PCI bus number
> and Y is the INTx.
>
> GPEX is currently used by riscv, aarch64/virt and x86/microvm machines.
> So, this change will alter the DSDT for those systems.
>
> [1] - ACPI 5.1: 6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/pci-host/gpex-acpi.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
> index f69413ea2c..391fabb8a8 100644
> --- a/hw/pci-host/gpex-acpi.c
> +++ b/hw/pci-host/gpex-acpi.c
> @@ -7,7 +7,8 @@
> #include "hw/pci/pcie_host.h"
> #include "hw/acpi/cxl.h"
>
> -static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
> +static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,
> + Aml *scope, uint8_t bus_num)
> {
> Aml *method, *crs;
> int i, slot_no;
> @@ -20,7 +21,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
> Aml *pkg = aml_package(4);
> aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
> aml_append(pkg, aml_int(i));
> - aml_append(pkg, aml_name("GSI%d", gsi));
> + aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi));
> aml_append(pkg, aml_int(0));
> aml_append(rt_pkg, pkg);
> }
> @@ -30,7 +31,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
> /* Create GSI link device */
> for (i = 0; i < PCI_NUM_PINS; i++) {
> uint32_t irqs = irq + i;
> - Aml *dev_gsi = aml_device("GSI%d", i);
> + Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i);
> aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
> crs = aml_resource_template();
> @@ -45,7 +46,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
> aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
> aml_append(dev_gsi, method);
> - aml_append(dev, dev_gsi);
> + aml_append(scope, dev_gsi);
> }
> }
>
> @@ -174,7 +175,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
> aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
> }
>
> - acpi_dsdt_add_pci_route_table(dev, cfg->irq);
> + acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num);
>
> /*
> * Resources defined for PXBs are composed of the following parts:
> @@ -205,7 +206,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
> aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
> aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
>
> - acpi_dsdt_add_pci_route_table(dev, cfg->irq);
> + acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0);
>
> method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
> aml_append(method, aml_return(aml_int(cfg->ecam.base)));
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
` (3 preceding siblings ...)
2024-07-15 17:11 ` [PATCH v3 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-15 17:11 ` [PATCH v3 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path Sunil V L
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
After PCI link devices are moved out of the scope of PCI root complex,
the DSDT files of machines which use GPEX, will change. So, update the
expected AML files with these changes for these machines.
Mainly, there are 2 changes.
1) Since the link devices are created now directly under _SB for all PCI
root bridges in the system, they should have unique names. So, instead
of GSIx, named those devices as LXXY where L means link, XX will have
PCI bus number and Y will have the INTx number (ex: L000 or L001). The
_PRT entries will also be updated to reflect this name change.
2) PCI link devices are moved from the scope of each PCI root bridge to
directly under _SB.
Below is the sample iASL difference for one such link device.
Scope (\_SB)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1F) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004F,
}
})
+ Device (L000)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, Zero) // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
{
Package (0x04)
{
0xFFFF,
Zero,
- GSI0,
+ L000,
Zero
},
.....
})
Device (GSI0)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Name (_CRS, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
}
}
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5196 bytes
.../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5282 bytes
tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6557 bytes
tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7679 bytes
tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5398 bytes
tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 3023 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 6 ------
7 files changed, 6 deletions(-)
diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/virt/DSDT
index c47503990715d389914fdf9c8bccb510761741ac..36d3e5d5a5e47359b6dcb3706f98b4f225677591 100644
GIT binary patch
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diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt b/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt
index aee6ba017cd730948bfa93e91551eb10a6809293..e6154d0355f84fdcc51387b4db8f9ee63acae4e9 100644
GIT binary patch
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diff --git a/tests/data/acpi/aarch64/virt/DSDT.memhp b/tests/data/acpi/aarch64/virt/DSDT.memhp
index bae36cdd397473afe3923c52f030641a5ab19d5d..33f011d6b635035a04c0b39ce9b4e219f7ae74b7 100644
GIT binary patch
delta 1923
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delta 1922
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diff --git a/tests/data/acpi/aarch64/virt/DSDT.pxb b/tests/data/acpi/aarch64/virt/DSDT.pxb
index fbd78f44c4785d19759daea909fe6d6f9a6e6b01..c0fdc6e9c1396cc2259dc4bc665ba023adcf4c9b 100644
GIT binary patch
literal 7679
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diff --git a/tests/data/acpi/aarch64/virt/DSDT.topology b/tests/data/acpi/aarch64/virt/DSDT.topology
index 501314c91be01d927fd125e0c72e919fdd85592e..029d03eecc4efddc001e5377e85ac8e831294362 100644
GIT binary patch
literal 5398
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diff --git a/tests/data/acpi/x86/microvm/DSDT.pcie b/tests/data/acpi/x86/microvm/DSDT.pcie
index 765f14ef3d1e54d3cadccbf0a880f8adb73b3f1f..8eacd21d6ecdf9a3cd3e4f03cf1b40748dcbf53e 100644
GIT binary patch
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literal 3023
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diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 9282ea0fb2..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,7 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/DSDT",
-"tests/data/acpi/aarch64/virt/DSDT.memhp",
-"tests/data/acpi/aarch64/virt/DSDT.topology",
-"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/aarch64/virt/DSDT.pxb",
-"tests/data/acpi/x86/microvm/DSDT.pcie",
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
` (4 preceding siblings ...)
2024-07-15 17:11 ` [PATCH v3 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-15 17:11 ` [PATCH v3 7/9] tests/acpi: Add empty ACPI data files for RISC-V Sunil V L
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
The expected ACPI AML files are moved now under ${arch}/{machine} path.
Hence, there is no need to search in old path which didn't have ${arch}.
Remove the code which searches for the expected AML files under old path
as well.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test.c | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index f4c4704bab..498e0e35d9 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -267,15 +267,6 @@ static void dump_aml_files(test_data *data, bool rebuild)
data->arch, data->machine,
sdt->aml, ext);
- /*
- * To keep test cases not failing before the DATA files are moved to
- * ${arch}/${machine} folder, add this check as well.
- */
- if (!g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
- aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir,
- data->machine, sdt->aml, ext);
- }
-
if (!g_file_test(aml_file, G_FILE_TEST_EXISTS) &&
sdt->aml_len == exp_sdt->aml_len &&
!memcmp(sdt->aml, exp_sdt->aml, sdt->aml_len)) {
@@ -412,11 +403,6 @@ static GArray *load_expected_aml(test_data *data)
try_again:
aml_file = g_strdup_printf("%s/%s/%s/%.4s%s", data_dir, data->arch,
data->machine, sdt->aml, ext);
- if (!g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
- aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
- sdt->aml, ext);
- }
-
if (verbosity_level >= 2) {
fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 7/9] tests/acpi: Add empty ACPI data files for RISC-V
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
` (5 preceding siblings ...)
2024-07-15 17:11 ` [PATCH v3 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-15 17:11 ` [PATCH v3 8/9] tests/qtest/bios-tables-test.c: Enable basic testing " Sunil V L
2024-07-15 17:11 ` [PATCH v3 9/9] tests/acpi: Add expected ACPI AML files " Sunil V L
8 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
As per process documented (steps 1-3) in bios-tables-test.c, add empty
AML data files for RISC-V ACPI tables and add the entries in
bios-tables-test-allowed-diff.h.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/data/acpi/riscv64/virt/APIC | 0
tests/data/acpi/riscv64/virt/DSDT | 0
tests/data/acpi/riscv64/virt/FACP | 0
tests/data/acpi/riscv64/virt/MCFG | 0
tests/data/acpi/riscv64/virt/RHCT | 0
tests/data/acpi/riscv64/virt/SPCR | 0
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++++++
7 files changed, 6 insertions(+)
create mode 100644 tests/data/acpi/riscv64/virt/APIC
create mode 100644 tests/data/acpi/riscv64/virt/DSDT
create mode 100644 tests/data/acpi/riscv64/virt/FACP
create mode 100644 tests/data/acpi/riscv64/virt/MCFG
create mode 100644 tests/data/acpi/riscv64/virt/RHCT
create mode 100644 tests/data/acpi/riscv64/virt/SPCR
diff --git a/tests/data/acpi/riscv64/virt/APIC b/tests/data/acpi/riscv64/virt/APIC
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/riscv64/virt/DSDT b/tests/data/acpi/riscv64/virt/DSDT
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/riscv64/virt/FACP b/tests/data/acpi/riscv64/virt/FACP
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/riscv64/virt/MCFG b/tests/data/acpi/riscv64/virt/MCFG
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/virt/SPCR
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..70474a097f 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,7 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/riscv64/virt/APIC",
+"tests/data/acpi/riscv64/virt/DSDT",
+"tests/data/acpi/riscv64/virt/FACP",
+"tests/data/acpi/riscv64/virt/MCFG",
+"tests/data/acpi/riscv64/virt/RHCT",
+"tests/data/acpi/riscv64/virt/SPCR",
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 8/9] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
` (6 preceding siblings ...)
2024-07-15 17:11 ` [PATCH v3 7/9] tests/acpi: Add empty ACPI data files for RISC-V Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
2024-07-15 17:11 ` [PATCH v3 9/9] tests/acpi: Add expected ACPI AML files " Sunil V L
8 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
Add basic ACPI table test case for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
tests/qtest/bios-tables-test.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 498e0e35d9..36e5c0adde 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1963,6 +1963,28 @@ static void test_acpi_microvm_acpi_erst(void)
}
#endif /* CONFIG_POSIX */
+static void test_acpi_riscv64_virt_tcg(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "riscv64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2",
+ .ram_start = 0x80000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ /*
+ * RHCT will have ISA string encoded. To reduce the effort
+ * of updating expected AML file for any new default ISA extension,
+ * use the profile rva22s64.
+ */
+ test_acpi_one("-cpu rva22s64 ", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
@@ -2441,6 +2463,10 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
}
}
+ } else if (strcmp(arch, "riscv64") == 0) {
+ if (has_tcg && qtest_has_device("virtio-blk-pci")) {
+ qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg);
+ }
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 9/9] tests/acpi: Add expected ACPI AML files for RISC-V
2024-07-15 17:11 [PATCH v3 0/9] RISC-V: ACPI: Namespace updates Sunil V L
` (7 preceding siblings ...)
2024-07-15 17:11 ` [PATCH v3 8/9] tests/qtest/bios-tables-test.c: Enable basic testing " Sunil V L
@ 2024-07-15 17:11 ` Sunil V L
8 siblings, 0 replies; 14+ messages in thread
From: Sunil V L @ 2024-07-15 17:11 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Michael S . Tsirkin,
Igor Mammedov, Ani Sinha, Sunil V L
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI AML data files for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
These are all new files being added for the first time. Hence, iASL diff
output is not added.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
---
tests/data/acpi/riscv64/virt/APIC | Bin 0 -> 116 bytes
tests/data/acpi/riscv64/virt/DSDT | Bin 0 -> 3576 bytes
tests/data/acpi/riscv64/virt/FACP | Bin 0 -> 276 bytes
tests/data/acpi/riscv64/virt/MCFG | Bin 0 -> 60 bytes
tests/data/acpi/riscv64/virt/RHCT | Bin 0 -> 332 bytes
tests/data/acpi/riscv64/virt/SPCR | Bin 0 -> 80 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 6 ------
7 files changed, 6 deletions(-)
diff --git a/tests/data/acpi/riscv64/virt/APIC b/tests/data/acpi/riscv64/virt/APIC
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..66a25dfd2d6ea2b607c024722b2eab95873a01e9 100644
GIT binary patch
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I#NvT*0o0BN0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/riscv64/virt/DSDT b/tests/data/acpi/riscv64/virt/DSDT
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6a33f5647ddd6de3a0f000f718b58f6fff44f0fd 100644
GIT binary patch
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HcmV?d00001
diff --git a/tests/data/acpi/riscv64/virt/FACP b/tests/data/acpi/riscv64/virt/FACP
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a5276b65ea8ce46cc9b40d96d98f0669c9089ed4 100644
GIT binary patch
literal 276
zcmZ>BbPf<<WME(ucJg=j2v%^42yj*a0-z8Bhz+8t3k1-OV?`GjD1M-;Zz#xa0OIBc
A0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/riscv64/virt/MCFG b/tests/data/acpi/riscv64/virt/MCFG
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..37eb923a9320f5573c0c2cdb90bd98409cc7eb6f 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?Y6aq@Te2v%^42yj*a0!E-1hz+8VfB}^KA4CHH3`GY4
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4f231735abad925435c3cd052e6641b1b4187278 100644
GIT binary patch
literal 332
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/virt/SPCR
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4da9daf65f71a13ac2b488d4e9728f194b569a43 100644
GIT binary patch
literal 80
zcmWFza1IJ!U|?X{>E!S15v<@85#X!<1dKp25F12;fdT`FDF9*%FmM4$c8~z`e;@#f
G!2kgKJqrN<
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 70474a097f..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,7 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/riscv64/virt/APIC",
-"tests/data/acpi/riscv64/virt/DSDT",
-"tests/data/acpi/riscv64/virt/FACP",
-"tests/data/acpi/riscv64/virt/MCFG",
-"tests/data/acpi/riscv64/virt/RHCT",
-"tests/data/acpi/riscv64/virt/SPCR",
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread