From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org, "Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH v3 09/19] ppc: Add has_smt_siblings property to CPUPPCState
Date: Wed, 17 Jul 2024 02:26:05 +1000 [thread overview]
Message-ID: <20240716162617.32161-10-npiggin@gmail.com> (raw)
In-Reply-To: <20240716162617.32161-1-npiggin@gmail.com>
The decision to branch out to a slower SMT path in instruction
emulation will become a bit more complicated with the way that
"big-core" topology that will be implemented in subsequent changes.
Hide these details from the wider CPU emulation code with a bool
has_smt_siblings flag that can be set by machine initialisation.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 3 ++-
hw/ppc/pnv_core.c | 3 +++
hw/ppc/spapr_cpu_core.c | 12 +++++++++---
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 417b284318..321ed2da75 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1248,6 +1248,7 @@ struct CPUArchState {
int access_type;
/* For SMT processors */
+ bool has_smt_siblings;
int core_index;
#if !defined(CONFIG_USER_ONLY)
@@ -1514,7 +1515,7 @@ struct PowerPCCPUClass {
static inline bool ppc_cpu_core_single_threaded(CPUState *cs)
{
- return cs->nr_threads == 1;
+ return !POWERPC_CPU(cs)->env.has_smt_siblings;
}
static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 7bda29b9c7..8cfa94fbfa 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -288,6 +288,9 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
cpu = POWERPC_CPU(obj);
pc->threads[i] = POWERPC_CPU(obj);
+ if (cc->nr_threads > 1) {
+ cpu->env.has_smt_siblings = true;
+ }
snprintf(name, sizeof(name), "thread[%d]", i);
object_property_add_child(OBJECT(pc), name, obj);
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 4e13e6993a..2c6eeb41a4 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -351,9 +351,15 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
qemu_register_reset(spapr_cpu_core_reset_handler, sc);
sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
- sc->threads[i] = spapr_create_vcpu(sc, i, errp);
- if (!sc->threads[i] ||
- !spapr_realize_vcpu(sc->threads[i], spapr, sc, i, errp)) {
+ PowerPCCPU *cpu;
+
+ cpu = spapr_create_vcpu(sc, i, errp);
+ sc->threads[i] = cpu;
+ if (cpu && cc->nr_threads > 1) {
+ cpu->env.has_smt_siblings = true;
+ }
+
+ if (!cpu || !spapr_realize_vcpu(cpu, spapr, sc, i, errp)) {
spapr_cpu_core_unrealize(dev);
return;
}
--
2.45.1
next prev parent reply other threads:[~2024-07-16 16:28 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-16 16:25 [PATCH v3 00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-16 16:25 ` [PATCH v3 01/19] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-16 16:55 ` Cédric Le Goater
2024-07-16 16:25 ` [PATCH v3 02/19] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-16 16:25 ` [PATCH v3 03/19] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 04/19] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 05/19] ppc/pnv: use class attribute to limit SMT threads for different machines Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 06/19] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 08/19] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-16 16:26 ` Nicholas Piggin [this message]
2024-07-16 16:26 ` [PATCH v3 10/19] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 11/19] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-16 16:53 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 12/19] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-16 16:53 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-16 16:51 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 15/19] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-16 16:51 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 16/19] system/cpus: Add cpu_pause() function Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 17/19] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-16 16:52 ` Cédric Le Goater
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