From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org, "Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH v3 05/19] ppc/pnv: use class attribute to limit SMT threads for different machines
Date: Wed, 17 Jul 2024 02:26:01 +1000 [thread overview]
Message-ID: <20240716162617.32161-6-npiggin@gmail.com> (raw)
In-Reply-To: <20240716162617.32161-1-npiggin@gmail.com>
Use a class attribute to specify the number of SMT threads per core
permitted for different machines, 8 for powernv8 and 4 for powernv9/10.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/pnv.h | 1 +
hw/ppc/pnv.c | 12 +++++++++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 476b136146..1993dededf 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -76,6 +76,7 @@ struct PnvMachineClass {
/*< public >*/
const char *compat;
int compat_size;
+ int max_smt_threads;
void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
void (*i2c_init)(PnvMachineState *pnv);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 7878fed43c..fde51ca946 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -899,6 +899,7 @@ static void pnv_init(MachineState *machine)
PnvMachineState *pnv = PNV_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
+ int max_smt_threads = pmc->max_smt_threads;
char *fw_filename;
long fw_size;
uint64_t chip_ram_start = 0;
@@ -997,17 +998,19 @@ static void pnv_init(MachineState *machine)
pnv->num_chips =
machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
- if (machine->smp.threads > 8) {
- error_report("Cannot support more than 8 threads/core "
- "on a powernv machine");
+ if (machine->smp.threads > max_smt_threads) {
+ error_report("Cannot support more than %d threads/core "
+ "on %s machine", max_smt_threads, mc->desc);
exit(1);
}
+
if (!is_power_of_2(machine->smp.threads)) {
error_report("Cannot support %d threads/core on a powernv"
"machine because it must be a power of 2",
machine->smp.threads);
exit(1);
}
+
/*
* TODO: should we decide on how many chips we can create based
* on #cores and Venice vs. Murano vs. Naples chip type etc...,
@@ -2490,6 +2493,7 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 8;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
@@ -2514,6 +2518,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 4;
pmc->dt_power_mgt = pnv_dt_power_mgt;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
@@ -2538,6 +2543,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 4;
pmc->dt_power_mgt = pnv_dt_power_mgt;
xfc->match_nvt = pnv10_xive_match_nvt;
--
2.45.1
next prev parent reply other threads:[~2024-07-16 16:28 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-16 16:25 [PATCH v3 00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-16 16:25 ` [PATCH v3 01/19] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-16 16:55 ` Cédric Le Goater
2024-07-16 16:25 ` [PATCH v3 02/19] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-16 16:25 ` [PATCH v3 03/19] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 04/19] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-16 16:26 ` Nicholas Piggin [this message]
2024-07-16 16:26 ` [PATCH v3 06/19] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 08/19] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 09/19] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 10/19] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 11/19] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-16 16:53 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 12/19] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-16 16:53 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-16 16:51 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 15/19] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-16 16:51 ` Cédric Le Goater
2024-07-16 16:26 ` [PATCH v3 16/19] system/cpus: Add cpu_pause() function Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 17/19] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-16 16:26 ` [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-16 16:52 ` Cédric Le Goater
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