From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Alistair Francis" <alistair@alistair23.me>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:STM32F205" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC orgate information
Date: Thu, 18 Jul 2024 14:49:22 +0800 [thread overview]
Message-ID: <20240718064925.1846074-13-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240718064925.1846074-1-jamin_lin@aspeedtech.com>
Currently, users can set the intc mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous bits number in the
same orgate. To reduce the enumerated device id definition,
create a new API to get the INTC orgate index and source bit number
if users only provide the start bus number of device.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 4257b5e8af..0bbd66110b 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -164,6 +164,11 @@ struct gic_intc_irq_info {
const int *ptr;
};
+struct gic_intc_orgate_info {
+ int index;
+ int int_num;
+};
+
static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
{128, aspeed_soc_ast2700_gic128_intcmap},
{129, NULL},
@@ -193,6 +198,27 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
}
+static void aspeed_soc_ast2700_get_intc_orgate(AspeedSoCState *s, int dev,
+ struct gic_intc_orgate_info *orgate_info)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
+ assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ orgate_info->index = i;
+ orgate_info->int_num = aspeed_soc_ast2700_gic_intcmap[i].ptr[dev];
+ return;
+ }
+ }
+
+ /*
+ * Invalid orgate index, device irq should be 128 to 136.
+ */
+ g_assert_not_reached();
+}
+
static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
unsigned int size)
{
--
2.34.1
next prev parent reply other threads:[~2024-07-18 6:51 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 6:49 [PATCH v1 00/15] support ADC and I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 01/15] aspeed/adc: Add AST2700 support Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 02/15] aspeed/soc: support ADC for AST2700 Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size Jamin Lin via
2024-07-18 7:59 ` Cédric Le Goater
2024-07-18 9:42 ` Jamin Lin
2024-07-18 13:19 ` Cédric Le Goater
2024-07-19 1:11 ` Jamin Lin
2024-07-19 6:21 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register memory region of I2C bus Jamin Lin via
2024-07-18 8:44 ` Cédric Le Goater
2024-07-18 9:44 ` Jamin Lin
2024-07-18 13:41 ` Cédric Le Goater
2024-07-26 6:00 ` Jamin Lin
2024-08-26 11:48 ` Cédric Le Goater
2024-08-27 1:09 ` 林建明
2024-07-18 6:49 ` [PATCH v1 05/15] hw/i2c/aspeed: rename the I2C class pool attribute to share_pool Jamin Lin via
2024-07-18 8:08 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 06/15] hw/i2c/aspeed: introduce a new bus pool buffer attribute in AspeedI2Cbus Jamin Lin via
2024-07-18 8:40 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 07/15] hw/i2c/aspeed: support discontinuous poll buffer memory region of I2C bus Jamin Lin via
2024-07-18 8:48 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 08/15] hw/i2c/aspeed: introduce a new dma_dram_offset attribute in AspeedI2Cbus Jamin Lin via
2024-07-19 9:03 ` Cédric Le Goater
2024-07-26 2:03 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 09/15] hw/i2c/aspeed: Add AST2700 support Jamin Lin via
2024-07-18 8:51 ` Cédric Le Goater
2024-07-18 9:35 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 10/15] hw/i2c/aspeed: support Tx/Rx buffer 64 bits address Jamin Lin via
2024-07-18 13:14 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 11/15] hw/i2c/aspeed: support high part dram offset for DMA 64 bits Jamin Lin via
2024-07-19 9:04 ` Cédric Le Goater
2024-07-18 6:49 ` Jamin Lin via [this message]
2024-07-19 9:19 ` [PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC orgate information Cédric Le Goater
2024-07-26 6:35 ` Jamin Lin
2024-07-26 7:00 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 13/15] aspeed/soc: support I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 14/15] aspeed: fix coding style Jamin Lin via
2024-07-18 8:53 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 15/15] aspeed: add tmp105 in i2c bus 0 for AST2700 Jamin Lin via
2024-07-18 8:55 ` Cédric Le Goater
2024-07-18 9:33 ` Jamin Lin
2024-07-18 16:18 ` [PATCH v1 00/15] support ADC and I2C " Cédric Le Goater
2024-07-19 6:24 ` Cédric Le Goater
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