From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Alistair Francis" <alistair@alistair23.me>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:STM32F205" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 02/15] aspeed/soc: support ADC for AST2700
Date: Thu, 18 Jul 2024 14:49:12 +0800 [thread overview]
Message-ID: <20240718064925.1846074-3-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240718064925.1846074-1-jamin_lin@aspeedtech.com>
Add ADC model for AST2700 ADC support.
The ADC controller registers base address is start at
0x14C0_0000 and its address space is 0x1000.
The ADC controller interrupt is connected to
GICINT130_INTC group at bit 16. The GIC IRQ is 130.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a9fb0d4b88..4257b5e8af 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -60,6 +60,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_SLIIO] = 0x14C1E000,
[ASPEED_GIC_DIST] = 0x12200000,
[ASPEED_GIC_REDIST] = 0x12280000,
+ [ASPEED_DEV_ADC] = 0x14C00000,
};
#define AST2700_MAX_IRQ 288
@@ -344,6 +345,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
+
+ snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
+ object_initialize_child(obj, "adc", &s->adc, typename);
}
/*
@@ -601,6 +605,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0,
sc->memmap[ASPEED_DEV_SLIIO]);
+ /* ADC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--
2.34.1
next prev parent reply other threads:[~2024-07-18 6:51 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 6:49 [PATCH v1 00/15] support ADC and I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 01/15] aspeed/adc: Add AST2700 support Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` Jamin Lin via [this message]
2024-07-18 7:51 ` [PATCH v1 02/15] aspeed/soc: support ADC for AST2700 Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size Jamin Lin via
2024-07-18 7:59 ` Cédric Le Goater
2024-07-18 9:42 ` Jamin Lin
2024-07-18 13:19 ` Cédric Le Goater
2024-07-19 1:11 ` Jamin Lin
2024-07-19 6:21 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register memory region of I2C bus Jamin Lin via
2024-07-18 8:44 ` Cédric Le Goater
2024-07-18 9:44 ` Jamin Lin
2024-07-18 13:41 ` Cédric Le Goater
2024-07-26 6:00 ` Jamin Lin
2024-08-26 11:48 ` Cédric Le Goater
2024-08-27 1:09 ` 林建明
2024-07-18 6:49 ` [PATCH v1 05/15] hw/i2c/aspeed: rename the I2C class pool attribute to share_pool Jamin Lin via
2024-07-18 8:08 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 06/15] hw/i2c/aspeed: introduce a new bus pool buffer attribute in AspeedI2Cbus Jamin Lin via
2024-07-18 8:40 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 07/15] hw/i2c/aspeed: support discontinuous poll buffer memory region of I2C bus Jamin Lin via
2024-07-18 8:48 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 08/15] hw/i2c/aspeed: introduce a new dma_dram_offset attribute in AspeedI2Cbus Jamin Lin via
2024-07-19 9:03 ` Cédric Le Goater
2024-07-26 2:03 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 09/15] hw/i2c/aspeed: Add AST2700 support Jamin Lin via
2024-07-18 8:51 ` Cédric Le Goater
2024-07-18 9:35 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 10/15] hw/i2c/aspeed: support Tx/Rx buffer 64 bits address Jamin Lin via
2024-07-18 13:14 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 11/15] hw/i2c/aspeed: support high part dram offset for DMA 64 bits Jamin Lin via
2024-07-19 9:04 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC orgate information Jamin Lin via
2024-07-19 9:19 ` Cédric Le Goater
2024-07-26 6:35 ` Jamin Lin
2024-07-26 7:00 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 13/15] aspeed/soc: support I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 14/15] aspeed: fix coding style Jamin Lin via
2024-07-18 8:53 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 15/15] aspeed: add tmp105 in i2c bus 0 for AST2700 Jamin Lin via
2024-07-18 8:55 ` Cédric Le Goater
2024-07-18 9:33 ` Jamin Lin
2024-07-18 16:18 ` [PATCH v1 00/15] support ADC and I2C " Cédric Le Goater
2024-07-19 6:24 ` Cédric Le Goater
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