From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Alistair Francis" <alistair@alistair23.me>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:STM32F205" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size
Date: Thu, 18 Jul 2024 14:49:13 +0800 [thread overview]
Message-ID: <20240718064925.1846074-4-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240718064925.1846074-1-jamin_lin@aspeedtech.com>
According to the datasheet of ASPEED SOCs,
an I2C controller owns 8KB of register space for AST2700,
owns 4KB of register space for AST2600, AST2500 and AST2400,
and owns 64KB of register space for AST1030.
It set the memory region size 4KB by default and it does not compatible
register space for AST2700.
Introduce a new class attribute to set the I2C controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/i2c/aspeed_i2c.c | 6 +++++-
include/hw/i2c/aspeed_i2c.h | 2 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index b43afd250d..7d5a53c4c0 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1014,7 +1014,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
- "aspeed.i2c", 0x1000);
+ "aspeed.i2c", aic->mem_size);
sysbus_init_mmio(sbd, &s->iomem);
for (i = 0; i < aic->num_busses; i++) {
@@ -1286,6 +1286,7 @@ static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data)
aic->pool_size = 0x800;
aic->pool_base = 0x800;
aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base;
+ aic->mem_size = 0x1000;
}
static const TypeInfo aspeed_2400_i2c_info = {
@@ -1320,6 +1321,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data)
aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
aic->check_sram = true;
aic->has_dma = true;
+ aic->mem_size = 0x1000;
}
static const TypeInfo aspeed_2500_i2c_info = {
@@ -1353,6 +1355,7 @@ static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data)
aic->pool_base = 0xC00;
aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base;
aic->has_dma = true;
+ aic->mem_size = 0x1000;
}
static const TypeInfo aspeed_2600_i2c_info = {
@@ -1376,6 +1379,7 @@ static void aspeed_1030_i2c_class_init(ObjectClass *klass, void *data)
aic->pool_base = 0xC00;
aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base;
aic->has_dma = true;
+ aic->mem_size = 0x10000;
}
static const TypeInfo aspeed_1030_i2c_info = {
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index a064479e59..065b636d29 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -283,7 +283,7 @@ struct AspeedI2CClass {
uint8_t *(*bus_pool_base)(AspeedI2CBus *);
bool check_sram;
bool has_dma;
-
+ uint64_t mem_size;
};
static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s)
--
2.34.1
next prev parent reply other threads:[~2024-07-18 6:51 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 6:49 [PATCH v1 00/15] support ADC and I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 01/15] aspeed/adc: Add AST2700 support Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 02/15] aspeed/soc: support ADC for AST2700 Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` Jamin Lin via [this message]
2024-07-18 7:59 ` [PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size Cédric Le Goater
2024-07-18 9:42 ` Jamin Lin
2024-07-18 13:19 ` Cédric Le Goater
2024-07-19 1:11 ` Jamin Lin
2024-07-19 6:21 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register memory region of I2C bus Jamin Lin via
2024-07-18 8:44 ` Cédric Le Goater
2024-07-18 9:44 ` Jamin Lin
2024-07-18 13:41 ` Cédric Le Goater
2024-07-26 6:00 ` Jamin Lin
2024-08-26 11:48 ` Cédric Le Goater
2024-08-27 1:09 ` 林建明
2024-07-18 6:49 ` [PATCH v1 05/15] hw/i2c/aspeed: rename the I2C class pool attribute to share_pool Jamin Lin via
2024-07-18 8:08 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 06/15] hw/i2c/aspeed: introduce a new bus pool buffer attribute in AspeedI2Cbus Jamin Lin via
2024-07-18 8:40 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 07/15] hw/i2c/aspeed: support discontinuous poll buffer memory region of I2C bus Jamin Lin via
2024-07-18 8:48 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 08/15] hw/i2c/aspeed: introduce a new dma_dram_offset attribute in AspeedI2Cbus Jamin Lin via
2024-07-19 9:03 ` Cédric Le Goater
2024-07-26 2:03 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 09/15] hw/i2c/aspeed: Add AST2700 support Jamin Lin via
2024-07-18 8:51 ` Cédric Le Goater
2024-07-18 9:35 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 10/15] hw/i2c/aspeed: support Tx/Rx buffer 64 bits address Jamin Lin via
2024-07-18 13:14 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 11/15] hw/i2c/aspeed: support high part dram offset for DMA 64 bits Jamin Lin via
2024-07-19 9:04 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC orgate information Jamin Lin via
2024-07-19 9:19 ` Cédric Le Goater
2024-07-26 6:35 ` Jamin Lin
2024-07-26 7:00 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 13/15] aspeed/soc: support I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 14/15] aspeed: fix coding style Jamin Lin via
2024-07-18 8:53 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 15/15] aspeed: add tmp105 in i2c bus 0 for AST2700 Jamin Lin via
2024-07-18 8:55 ` Cédric Le Goater
2024-07-18 9:33 ` Jamin Lin
2024-07-18 16:18 ` [PATCH v1 00/15] support ADC and I2C " Cédric Le Goater
2024-07-19 6:24 ` Cédric Le Goater
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