From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Alistair Francis" <alistair@alistair23.me>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register memory region of I2C bus
Date: Thu, 18 Jul 2024 14:49:14 +0800 [thread overview]
Message-ID: <20240718064925.1846074-5-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240718064925.1846074-1-jamin_lin@aspeedtech.com>
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0x37F: Device 2
0x400 - 0x47F: Device 3
0x500 - 0x57F: Device 4
0x600 - 0x67F: Device 5
0x700 - 0x77F: Device 6
0x800 - 0x87F: Device 7
0x900 - 0x97F: Device 8
0xA00 - 0xA7F: Device 9
0xB00 - 0xB7F: Device 10
0xC00 - 0xC7F: Device 11
0xD00 - 0xD7F: Device 12
0xE00 - 0xE7F: Device 13
0xF00 – 0xF7F: Device 14
0x1000 – 0x107F: Device 15
Introduce a new class attribute to make user set each I2C bus gap size.
Update formula to create all I2C bus register memory regions.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/i2c/aspeed_i2c.c | 3 ++-
include/hw/i2c/aspeed_i2c.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 7d5a53c4c0..462ad78a13 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1011,6 +1011,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedI2CState *s = ASPEED_I2C(dev);
AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
+ uint32_t reg_offset = aic->reg_size + aic->reg_gap_size;
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
@@ -1033,7 +1034,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
return;
}
- memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset),
+ memory_region_add_subregion(&s->iomem, reg_offset * (i + offset),
&s->busses[i].mr);
}
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 065b636d29..422ee0e298 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -275,6 +275,7 @@ struct AspeedI2CClass {
uint8_t num_busses;
uint8_t reg_size;
+ uint32_t reg_gap_size;
uint8_t gap;
qemu_irq (*bus_get_irq)(AspeedI2CBus *);
--
2.34.1
next prev parent reply other threads:[~2024-07-18 6:51 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 6:49 [PATCH v1 00/15] support ADC and I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 01/15] aspeed/adc: Add AST2700 support Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 02/15] aspeed/soc: support ADC for AST2700 Jamin Lin via
2024-07-18 7:51 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size Jamin Lin via
2024-07-18 7:59 ` Cédric Le Goater
2024-07-18 9:42 ` Jamin Lin
2024-07-18 13:19 ` Cédric Le Goater
2024-07-19 1:11 ` Jamin Lin
2024-07-19 6:21 ` Cédric Le Goater
2024-07-18 6:49 ` Jamin Lin via [this message]
2024-07-18 8:44 ` [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register memory region of I2C bus Cédric Le Goater
2024-07-18 9:44 ` Jamin Lin
2024-07-18 13:41 ` Cédric Le Goater
2024-07-26 6:00 ` Jamin Lin
2024-08-26 11:48 ` Cédric Le Goater
2024-08-27 1:09 ` 林建明
2024-07-18 6:49 ` [PATCH v1 05/15] hw/i2c/aspeed: rename the I2C class pool attribute to share_pool Jamin Lin via
2024-07-18 8:08 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 06/15] hw/i2c/aspeed: introduce a new bus pool buffer attribute in AspeedI2Cbus Jamin Lin via
2024-07-18 8:40 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 07/15] hw/i2c/aspeed: support discontinuous poll buffer memory region of I2C bus Jamin Lin via
2024-07-18 8:48 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 08/15] hw/i2c/aspeed: introduce a new dma_dram_offset attribute in AspeedI2Cbus Jamin Lin via
2024-07-19 9:03 ` Cédric Le Goater
2024-07-26 2:03 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 09/15] hw/i2c/aspeed: Add AST2700 support Jamin Lin via
2024-07-18 8:51 ` Cédric Le Goater
2024-07-18 9:35 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 10/15] hw/i2c/aspeed: support Tx/Rx buffer 64 bits address Jamin Lin via
2024-07-18 13:14 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 11/15] hw/i2c/aspeed: support high part dram offset for DMA 64 bits Jamin Lin via
2024-07-19 9:04 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC orgate information Jamin Lin via
2024-07-19 9:19 ` Cédric Le Goater
2024-07-26 6:35 ` Jamin Lin
2024-07-26 7:00 ` Jamin Lin
2024-07-18 6:49 ` [PATCH v1 13/15] aspeed/soc: support I2C for AST2700 Jamin Lin via
2024-07-18 6:49 ` [PATCH v1 14/15] aspeed: fix coding style Jamin Lin via
2024-07-18 8:53 ` Cédric Le Goater
2024-07-18 6:49 ` [PATCH v1 15/15] aspeed: add tmp105 in i2c bus 0 for AST2700 Jamin Lin via
2024-07-18 8:55 ` Cédric Le Goater
2024-07-18 9:33 ` Jamin Lin
2024-07-18 16:18 ` [PATCH v1 00/15] support ADC and I2C " Cédric Le Goater
2024-07-19 6:24 ` Cédric Le Goater
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