From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com,
jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
Zhenzhong Duan <zhenzhong.duan@intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: [PATCH v1 10/17] intel_iommu: Process PASID-based iotlb invalidation
Date: Thu, 18 Jul 2024 16:16:29 +0800 [thread overview]
Message-ID: <20240718081636.879544-11-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com>
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 45 ++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index cf0f176e06..7dd8176e86 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -470,6 +470,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \
VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL)
+#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL)
+#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1)
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 8d47e5ba78..8ebb6dbd7d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -322,6 +322,28 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
return (entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb;
}
+static gboolean vtd_hash_remove_by_page_piotlb(gpointer key, gpointer value,
+ gpointer user_data)
+{
+ VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
+ VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
+ uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
+ uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
+
+ /*
+ * According to spec, PASID-based-IOTLB Invalidation in page granularity
+ * doesn't invalidate IOTLB entries caching second-stage (PGTT=010b)
+ * or pass-through (PGTT=100b) mappings. Nested isn't supported yet,
+ * so only need to check first-stage (PGTT=001b) mappings.
+ */
+ if (entry->pgtt != VTD_SM_PASID_ENTRY_FLT) {
+ return false;
+ }
+
+ return entry->domain_id == info->domain_id && entry->pasid == info->pasid &&
+ ((entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb);
+}
+
/* Reset all the gen of VTDAddressSpace to zero and set the gen of
* IntelIOMMUState to 1. Must be called with IOMMU lock held.
*/
@@ -2886,11 +2908,30 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
}
}
+static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
+ uint32_t pasid, hwaddr addr, uint8_t am,
+ bool ih)
+{
+ VTDIOTLBPageInvInfo info;
+
+ info.domain_id = domain_id;
+ info.pasid = pasid;
+ info.addr = addr;
+ info.mask = ~((1 << am) - 1);
+
+ vtd_iommu_lock(s);
+ g_hash_table_foreach_remove(s->iotlb,
+ vtd_hash_remove_by_page_piotlb, &info);
+ vtd_iommu_unlock(s);
+}
+
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
uint16_t domain_id;
uint32_t pasid;
+ uint8_t am;
+ hwaddr addr;
if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) ||
(inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) {
@@ -2907,6 +2948,10 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
break;
case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+ am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
+ addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
+ vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am,
+ VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]));
break;
default:
--
2.34.1
next prev parent reply other threads:[~2024-07-18 8:21 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 8:16 [PATCH v1 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-07-23 7:12 ` CLEMENT MATHIEU--DRIF
2024-07-29 7:39 ` Yi Liu
2024-07-29 8:42 ` Michael S. Tsirkin
2024-07-29 9:39 ` Yi Liu
2024-07-18 8:16 ` [PATCH v1 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-07-18 9:06 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-07-18 9:02 ` CLEMENT MATHIEU--DRIF
2024-07-19 2:47 ` Duan, Zhenzhong
2024-07-19 3:22 ` Yi Liu
2024-07-19 3:37 ` Duan, Zhenzhong
2024-07-19 3:39 ` Duan, Zhenzhong
2024-07-19 4:26 ` CLEMENT MATHIEU--DRIF
2024-07-23 7:12 ` CLEMENT MATHIEU--DRIF
2024-07-23 8:50 ` Duan, Zhenzhong
2024-07-19 4:21 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-07-23 16:02 ` CLEMENT MATHIEU--DRIF
2024-07-24 2:59 ` Duan, Zhenzhong
2024-07-24 5:16 ` CLEMENT MATHIEU--DRIF
2024-07-24 5:19 ` Duan, Zhenzhong
2024-07-18 8:16 ` [PATCH v1 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-07-23 7:12 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` Zhenzhong Duan [this message]
2024-07-23 16:18 ` [PATCH v1 10/17] intel_iommu: Process PASID-based " CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic Zhenzhong Duan
2024-07-24 8:35 ` CLEMENT MATHIEU--DRIF
2024-07-24 8:42 ` Duan, Zhenzhong
2024-07-18 8:16 ` [PATCH v1 12/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 13/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-07-24 5:45 ` CLEMENT MATHIEU--DRIF
2024-07-24 6:04 ` CLEMENT MATHIEU--DRIF
2024-07-24 6:07 ` Duan, Zhenzhong
2024-07-24 6:11 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Zhenzhong Duan
2024-07-18 9:14 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option Zhenzhong Duan
2024-07-18 9:25 ` CLEMENT MATHIEU--DRIF
2024-07-19 2:53 ` Duan, Zhenzhong
2024-07-19 4:23 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-07-24 5:58 ` CLEMENT MATHIEU--DRIF
2024-07-24 6:14 ` Duan, Zhenzhong
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