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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
	eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com,
	jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
	joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
	kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Zhenzhong Duan" <zhenzhong.duan@intel.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>
Subject: [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic
Date: Thu, 18 Jul 2024 16:16:30 +0800	[thread overview]
Message-ID: <20240718081636.879544-12-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com>

From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>

This piece of code can be shared by both IOTLB invalidation and
PASID-based IOTLB invalidation

No functional changes intended.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
 hw/i386/intel_iommu.c | 57 +++++++++++++++++++++++++------------------
 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 8ebb6dbd7d..4d5a457f92 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2975,13 +2975,43 @@ static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
     return true;
 }
 
+static void do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as,
+                                     bool size, hwaddr addr)
+{
+    /*
+     * According to ATS spec table 2.4:
+     * S = 0, bits 15:12 = xxxx     range size: 4K
+     * S = 1, bits 15:12 = xxx0     range size: 8K
+     * S = 1, bits 15:12 = xx01     range size: 16K
+     * S = 1, bits 15:12 = x011     range size: 32K
+     * S = 1, bits 15:12 = 0111     range size: 64K
+     * ...
+     */
+
+    IOMMUTLBEvent event;
+    uint64_t sz;
+
+    if (size) {
+        sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
+        addr &= ~(sz - 1);
+    } else {
+        sz = VTD_PAGE_SIZE;
+    }
+
+    event.type = IOMMU_NOTIFIER_DEVIOTLB_UNMAP;
+    event.entry.target_as = &vtd_dev_as->as;
+    event.entry.addr_mask = sz - 1;
+    event.entry.iova = addr;
+    event.entry.perm = IOMMU_NONE;
+    event.entry.translated_addr = 0;
+    memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
+}
+
 static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
                                           VTDInvDesc *inv_desc)
 {
     VTDAddressSpace *vtd_dev_as;
-    IOMMUTLBEvent event;
     hwaddr addr;
-    uint64_t sz;
     uint16_t sid;
     bool size;
 
@@ -3006,28 +3036,7 @@ static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
         goto done;
     }
 
-    /* According to ATS spec table 2.4:
-     * S = 0, bits 15:12 = xxxx     range size: 4K
-     * S = 1, bits 15:12 = xxx0     range size: 8K
-     * S = 1, bits 15:12 = xx01     range size: 16K
-     * S = 1, bits 15:12 = x011     range size: 32K
-     * S = 1, bits 15:12 = 0111     range size: 64K
-     * ...
-     */
-    if (size) {
-        sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
-        addr &= ~(sz - 1);
-    } else {
-        sz = VTD_PAGE_SIZE;
-    }
-
-    event.type = IOMMU_NOTIFIER_DEVIOTLB_UNMAP;
-    event.entry.target_as = &vtd_dev_as->as;
-    event.entry.addr_mask = sz - 1;
-    event.entry.iova = addr;
-    event.entry.perm = IOMMU_NONE;
-    event.entry.translated_addr = 0;
-    memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
+    do_invalidate_device_tlb(vtd_dev_as, size, addr);
 
 done:
     return true;
-- 
2.34.1



  parent reply	other threads:[~2024-07-18  8:21 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-18  8:16 [PATCH v1 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-07-23  7:12   ` CLEMENT MATHIEU--DRIF
2024-07-29  7:39   ` Yi Liu
2024-07-29  8:42     ` Michael S. Tsirkin
2024-07-29  9:39       ` Yi Liu
2024-07-18  8:16 ` [PATCH v1 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-07-18  9:06   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-07-18  9:02   ` CLEMENT MATHIEU--DRIF
2024-07-19  2:47     ` Duan, Zhenzhong
2024-07-19  3:22       ` Yi Liu
2024-07-19  3:37         ` Duan, Zhenzhong
2024-07-19  3:39           ` Duan, Zhenzhong
2024-07-19  4:26             ` CLEMENT MATHIEU--DRIF
2024-07-23  7:12             ` CLEMENT MATHIEU--DRIF
2024-07-23  8:50               ` Duan, Zhenzhong
2024-07-19  4:21       ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-07-23 16:02   ` CLEMENT MATHIEU--DRIF
2024-07-24  2:59     ` Duan, Zhenzhong
2024-07-24  5:16       ` CLEMENT MATHIEU--DRIF
2024-07-24  5:19         ` Duan, Zhenzhong
2024-07-18  8:16 ` [PATCH v1 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-07-23  7:12   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-07-23 16:18   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` Zhenzhong Duan [this message]
2024-07-24  8:35   ` [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic CLEMENT MATHIEU--DRIF
2024-07-24  8:42     ` Duan, Zhenzhong
2024-07-18  8:16 ` [PATCH v1 12/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 13/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-07-24  5:45   ` CLEMENT MATHIEU--DRIF
2024-07-24  6:04     ` CLEMENT MATHIEU--DRIF
2024-07-24  6:07       ` Duan, Zhenzhong
2024-07-24  6:11         ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Zhenzhong Duan
2024-07-18  9:14   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option Zhenzhong Duan
2024-07-18  9:25   ` CLEMENT MATHIEU--DRIF
2024-07-19  2:53     ` Duan, Zhenzhong
2024-07-19  4:23       ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-07-24  5:58   ` CLEMENT MATHIEU--DRIF
2024-07-24  6:14     ` Duan, Zhenzhong

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