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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
	eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com,
	jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
	joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
	kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
	Zhenzhong Duan <zhenzhong.duan@intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode
Date: Thu, 18 Jul 2024 16:16:34 +0800	[thread overview]
Message-ID: <20240718081636.879544-16-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com>

According to VTD spec, stage-1 page table could support 4-level and
5-level paging.

However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.

So default aw_bits to 48 in scalable modern mode. In other cases,
it is still default to 39 for compatibility.

Add a check to ensure user specified value is 48 in modern mode
for now.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
 include/hw/i386/intel_iommu.h |  2 +-
 hw/i386/intel_iommu.c         | 16 +++++++++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index b843d069cc..48134bda11 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -45,7 +45,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
 #define DMAR_REG_SIZE               0x230
 #define VTD_HOST_AW_39BIT           39
 #define VTD_HOST_AW_48BIT           48
-#define VTD_HOST_ADDRESS_WIDTH      VTD_HOST_AW_39BIT
+#define VTD_HOST_AW_AUTO            0xff
 #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
 
 #define DMAR_REPORT_F_INTR          (1)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c0116497b1..2804c3628a 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3768,7 +3768,7 @@ static Property vtd_properties[] = {
                             ON_OFF_AUTO_AUTO),
     DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
     DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
-                      VTD_HOST_ADDRESS_WIDTH),
+                      VTD_HOST_AW_AUTO),
     DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
     DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
     DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
@@ -4686,6 +4686,14 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
         }
     }
 
+    if (s->aw_bits == VTD_HOST_AW_AUTO) {
+        if (s->scalable_modern) {
+            s->aw_bits = VTD_HOST_AW_48BIT;
+        } else {
+            s->aw_bits = VTD_HOST_AW_39BIT;
+        }
+    }
+
     if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
         (s->aw_bits != VTD_HOST_AW_48BIT) &&
         !s->scalable_modern) {
@@ -4694,6 +4702,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
         return false;
     }
 
+    if ((s->aw_bits != VTD_HOST_AW_48BIT) && s->scalable_modern) {
+        error_setg(errp, "Supported values for aw-bits are: %d",
+                   VTD_HOST_AW_48BIT);
+        return false;
+    }
+
     if (s->scalable_mode && !s->dma_drain) {
         error_setg(errp, "Need to set dma_drain for scalable mode");
         return false;
-- 
2.34.1



  parent reply	other threads:[~2024-07-18  8:21 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-18  8:16 [PATCH v1 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-07-23  7:12   ` CLEMENT MATHIEU--DRIF
2024-07-29  7:39   ` Yi Liu
2024-07-29  8:42     ` Michael S. Tsirkin
2024-07-29  9:39       ` Yi Liu
2024-07-18  8:16 ` [PATCH v1 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-07-18  9:06   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-07-18  9:02   ` CLEMENT MATHIEU--DRIF
2024-07-19  2:47     ` Duan, Zhenzhong
2024-07-19  3:22       ` Yi Liu
2024-07-19  3:37         ` Duan, Zhenzhong
2024-07-19  3:39           ` Duan, Zhenzhong
2024-07-19  4:26             ` CLEMENT MATHIEU--DRIF
2024-07-23  7:12             ` CLEMENT MATHIEU--DRIF
2024-07-23  8:50               ` Duan, Zhenzhong
2024-07-19  4:21       ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-07-23 16:02   ` CLEMENT MATHIEU--DRIF
2024-07-24  2:59     ` Duan, Zhenzhong
2024-07-24  5:16       ` CLEMENT MATHIEU--DRIF
2024-07-24  5:19         ` Duan, Zhenzhong
2024-07-18  8:16 ` [PATCH v1 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-07-23  7:12   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-07-23 16:18   ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic Zhenzhong Duan
2024-07-24  8:35   ` CLEMENT MATHIEU--DRIF
2024-07-24  8:42     ` Duan, Zhenzhong
2024-07-18  8:16 ` [PATCH v1 12/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 13/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-07-18  8:16 ` [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-07-24  5:45   ` CLEMENT MATHIEU--DRIF
2024-07-24  6:04     ` CLEMENT MATHIEU--DRIF
2024-07-24  6:07       ` Duan, Zhenzhong
2024-07-24  6:11         ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` Zhenzhong Duan [this message]
2024-07-18  9:14   ` [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option Zhenzhong Duan
2024-07-18  9:25   ` CLEMENT MATHIEU--DRIF
2024-07-19  2:53     ` Duan, Zhenzhong
2024-07-19  4:23       ` CLEMENT MATHIEU--DRIF
2024-07-18  8:16 ` [PATCH v1 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-07-24  5:58   ` CLEMENT MATHIEU--DRIF
2024-07-24  6:14     ` Duan, Zhenzhong

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