[PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU

[LIU Zhiwei <zhiwei_liu@linux.alibaba.com>]

This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.

This patch set has been tested with 6.9.0 Linux Image.
And add an avocado tuxrun test in tests/avocado.

v6:
  Use TUXRUN test case instead of boot_linux_console
  Add any32 and max32 cpu for RV64 QEMU 

v5:
  Rebase to master and add tags  

v4:
  Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
  Avocado: Add "if=none" to "-drive" option in QEMU command line

v3:
  Rebase to the master branch

v2:
  Remove the line that was inadvertently left in PATCH v1 4/6.
  Add an avocado test.

v1:
  https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html


LIU Zhiwei (2):
  target/riscv: Add any32 and max32 CPU for RV64 QEMU
  tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU

TANG Tiancheng (6):
  target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
  target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
  target/riscv: Correct SXL return value for RV32 in RV64 QEMU
  target/riscv: Detect sxl to set bit width for RV32 in RV64
  target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
  target/riscv: Enable RV32 CPU support in RV64 QEMU

 configs/targets/riscv64-softmmu.mak |  2 +-
 hw/riscv/boot.c                     | 35 +++++++++++++++++++----------
 hw/riscv/sifive_u.c                 |  3 ++-
 include/hw/riscv/boot.h             |  4 +++-
 include/hw/riscv/boot_opensbi.h     | 29 ++++++++++++++++++++++++
 target/riscv/cpu-qom.h              |  2 ++
 target/riscv/cpu.c                  | 30 +++++++++++++++++--------
 target/riscv/cpu.h                  |  5 ++++-
 target/riscv/cpu_helper.c           | 25 +++++++++++++++------
 target/riscv/pmp.c                  |  2 +-
 tests/avocado/tuxrun_baselines.py   | 16 +++++++++++++
 11 files changed, 120 insertions(+), 33 deletions(-)

-- 
2.25.1