From: "Michael S. Tsirkin" <mst@redhat.com>
To: Yee Li <seven.yi.lee@gmail.com>
Cc: jasowang@redhat.com, pbonzini@redhat.com,
richard.henderson@linaro.org, eduardo@habkost.net,
qemu-devel@nongnu.org
Subject: Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW
Date: Sat, 20 Jul 2024 14:28:56 -0400 [thread overview]
Message-ID: <20240720142728-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <CALX8JfT5ecx4qQTsBMdFAqS-r4FoBd0T5WQFGr0MwYnAMo+Meg@mail.gmail.com>
On Thu, Jul 04, 2024 at 02:54:00PM +0800, Yee Li wrote:
> Sorry, the patch missing "(( ))"
> Replace "& VTD_IQA_QS" with "& (VTD_IQA_QS | VTD_IQA_DW_MASK))" is correct.
> Revised patch as follows,
>
So submit it properly.
Also, how did you test the patch?
> Signed-off-by: yeeli <seven.yi.lee@gmail.com>
> ---
> hw/i386/intel_iommu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 37c21a0aec..23562ba26b 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque,
> hwaddr addr, unsigned size)
>
> /* Invalidation Queue Address Register, 64-bit */
> case DMAR_IQA_REG:
> - val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
> + val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & (VTD_IQA_QS
> + | VTD_IQA_DW_MASK));
This is a very messy way to write this.
Align things properly pls.
> if (size == 4) {
> val = val & ((1ULL << 32) - 1);
> }
> --
> 2.34.1
>
> YeeLi <seven.yi.lee@gmail.com> 于2024年7月4日周四 11:53写道:
> >
> > From: yeeli <seven.yi.lee@gmail.com>
> >
> > When dmar_readq or devmem2 read the DW of IQA always 0UL because
> > "& VTD_IQA_QS". So, try to fix it.
> >
> > case:
> > after vtd_mem_write
> > IQA val: 0x100206801
> >
> > after vtd_mem_read
> > IQA val: 0x100206001
> >
> > Signed-off-by: yeeli <seven.yi.lee@gmail.com>
> > ---
> > hw/i386/intel_iommu.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 37c21a0aec..e230a45940 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
> >
> > /* Invalidation Queue Address Register, 64-bit */
> > case DMAR_IQA_REG:
> > - val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
> > + val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS
> > + | VTD_IQA_DW_MASK);
> > if (size == 4) {
> > val = val & ((1ULL << 32) - 1);
> > }
> > --
> > 2.34.1
> >
next prev parent reply other threads:[~2024-07-20 18:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-04 3:53 [PATCH] intel-iommu: fix Read DMAR IQA REG DW YeeLi
2024-07-04 6:54 ` Yee Li
2024-07-20 18:28 ` Michael S. Tsirkin [this message]
2024-07-20 18:29 ` Michael S. Tsirkin
2024-07-23 2:40 ` Yee Li
2024-07-23 3:02 ` Yee Li
2024-07-23 8:05 ` Yi Liu
2024-07-24 6:34 ` Yee Li
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