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[5.90.113.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a721b7sm89920945e9.27.2024.07.20.11.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Jul 2024 11:38:45 -0700 (PDT) Date: Sat, 20 Jul 2024 14:38:42 -0400 From: "Michael S. Tsirkin" To: Bernhard Beschow Cc: qemu-devel@nongnu.org, Markus Armbruster , =?iso-8859-1?Q?Herv=E9?= Poussineau , Marcel Apfelbaum , Peter Maydell , Aurelien Jarno , Jiaxun Yang , qemu-ppc@nongnu.org, Mark Cave-Ayland , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , BALATON Zoltan , Huacai Chen Subject: Re: [PATCH 0/3] Resolve vt82c686 and piix4 qemu_irq memory leaks Message-ID: <20240720143745-mutt-send-email-mst@kernel.org> References: <20240704205854.18537-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240704205854.18537-1-shentey@gmail.com> Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jul 04, 2024 at 10:58:51PM +0200, Bernhard Beschow wrote: > This series first turns vt82c686's "INTR" pin into a named GPIO for better > comprehensibility. It then continues fixing qemu_irq memory leaks in vt82c686 > and piix4 by connecting out IRQs of the south bridges before they get realized. > This approach is already used in the pc machines after it had been discussed at > KVM forum `23. > > Observe that out IRQs are callbacks such as an INTR IRQ handler in a CPU which a > south bridge wants to trigger. If, as an implementation detail, the south bridge > wants to pass this callback to a child device, such as the PIC, then this > callback must be known to the south bridge before it gets realized. Otherwise > board code had to wire the PIC device itself, breaking encapsulation. This means > that qdev_connect_gpio_out*() has to be called before realize() which this > series implements. Another way to look at it is that callbacks apparently are > resouces such as memory regions which are also populated before realize(). > > Please check if above paragraph makes sense. > > Best regards, > Bernhard Bernhard, do you intend to resolve Zoltan's comments on this patchset? Thanks! > See also: > * https://lore.kernel.org/qemu-devel/0FFB5FD2-08CE-4CEC-9001-E7AC24407A44@gmail. > com/ > * "Remove intermediate IRQ forwarder" patches in > https://lore.kernel.org/qemu-devel/20230210163744.32182-1-philmd@linaro.org/ > > Testing done: > * Boot amigaone machine into Linux > * Boot pegasos2 machine into MorphOS > * Start fuloong2e machine and check that it doesn't abort > * Boot malta machine with https://people.debian.org/~gio/dqib/ > > Bernhard Beschow (3): > hw/isa/vt82c686: Turn "intr" irq into a named gpio > hw/isa/vt82c686: Resolve intermediate IRQ forwarder > hw/isa/piix: Resolve intermediate IRQ forwarder > > hw/isa/piix.c | 13 ++----------- > hw/isa/vt82c686.c | 12 ++---------- > hw/mips/fuloong2e.c | 2 +- > hw/mips/malta.c | 4 +--- > hw/ppc/amigaone.c | 8 ++++---- > hw/ppc/pegasos2.c | 4 ++-- > 6 files changed, 12 insertions(+), 31 deletions(-) > > -- > 2.45.2 >