From: Andrew Jones <ajones@ventanamicro.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com, philmd@linaro.org,
alex.bennee@linaro.org
Subject: Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
Date: Wed, 24 Jul 2024 10:01:18 -0500 [thread overview]
Message-ID: <20240724-ef8cf69388fb767b6710b48f@orel> (raw)
In-Reply-To: <20240719231149.1364-8-zhiwei_liu@linux.alibaba.com>
On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is that
> we want to follow the RISC-V custom where addw instruction doesn't
> exist in RV32 CPU.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu-qom.h | 2 ++
> target/riscv/cpu.c | 13 ++++++++-----
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 3670cfe6d9..9f91743b78 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -31,6 +31,8 @@
>
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
> +#define TYPE_RISCV_CPU_ANY32 RISCV_CPU_TYPE_NAME("any32")
'any' is on its way out[1], so we probably shouldn't bother adding any32
at all with this series
[1] https://lore.kernel.org/all/20240724130717.95629-1-philmd@linaro.org/
Thanks,
drew
next prev parent reply other threads:[~2024-07-24 15:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-19 23:11 [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 6/8] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for " LIU Zhiwei
2024-07-20 9:24 ` Daniel Henrique Barboza
2024-07-24 15:01 ` Andrew Jones [this message]
2024-07-25 1:53 ` LIU Zhiwei
2024-07-24 18:22 ` Peter Maydell
2024-07-19 23:11 ` [PATCH v6 8/8] tests/avocado: Boot Linux for RV32 cpu on " LIU Zhiwei
2024-07-20 9:24 ` Daniel Henrique Barboza
2024-07-25 10:27 ` Alex Bennée
2024-07-24 2:44 ` [PATCH v6 0/8] target/riscv: Expose RV32 cpu to " Alistair Francis
2024-07-25 7:01 ` Philippe Mathieu-Daudé
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