From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-ppc@nongnu.org, BALATON Zoltan <balaton@eik.bme.hu>
Subject: [PULL 89/96] target/ppc: Remove bat_size_prot()
Date: Fri, 26 Jul 2024 09:54:02 +1000 [thread overview]
Message-ID: <20240725235410.451624-90-npiggin@gmail.com> (raw)
In-Reply-To: <20240725235410.451624-1-npiggin@gmail.com>
From: BALATON Zoltan <balaton@eik.bme.hu>
There is already a hash32_bat_prot() function that does most if this
and the rest can be inlined. Export hash32_bat_prot() and rename it to
ppc_hash32_bat_prot() to match other functions and use it in
get_bat_6xx_tlb().
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu-hash32.c | 18 +-------------
target/ppc/mmu-hash32.h | 14 +++++++++++
target/ppc/mmu_common.c | 52 ++++++++++-------------------------------
3 files changed, 27 insertions(+), 57 deletions(-)
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 160311de87..6f0f0bbb00 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -48,22 +48,6 @@ static target_ulong hash32_bat_size(int mmu_idx,
return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
}
-static int hash32_bat_prot(PowerPCCPU *cpu,
- target_ulong batu, target_ulong batl)
-{
- int pp, prot;
-
- prot = 0;
- pp = batl & BATL32_PP;
- if (pp != 0) {
- prot = PAGE_READ | PAGE_EXEC;
- if (pp == 0x2) {
- prot |= PAGE_WRITE;
- }
- }
- return prot;
-}
-
static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea,
MMUAccessType access_type, int *prot,
int mmu_idx)
@@ -95,7 +79,7 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea,
if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
hwaddr raddr = (batl & mask) | (ea & ~mask);
- *prot = hash32_bat_prot(cpu, batu, batl);
+ *prot = ppc_hash32_bat_prot(batu, batl);
return raddr & TARGET_PAGE_MASK;
}
diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h
index 5902cf8333..bd75f7d647 100644
--- a/target/ppc/mmu-hash32.h
+++ b/target/ppc/mmu-hash32.h
@@ -143,6 +143,20 @@ static inline int ppc_hash32_prot(bool key, int pp, bool nx)
return nx ? prot : prot | PAGE_EXEC;
}
+static inline int ppc_hash32_bat_prot(target_ulong batu, target_ulong batl)
+{
+ int prot = 0;
+ int pp = batl & BATL32_PP;
+
+ if (pp) {
+ prot = PAGE_READ | PAGE_EXEC;
+ if (pp == 0x2) {
+ prot |= PAGE_WRITE;
+ }
+ }
+ return prot;
+}
+
typedef struct {
uint32_t pte0, pte1;
} ppc_hash_pte32_t;
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index aa002bba35..624ed51a92 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -193,40 +193,13 @@ static int ppc6xx_tlb_check(CPUPPCState *env, hwaddr *raddr, int *prot,
return ret;
}
-/* Perform BAT hit & translation */
-static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,
- int *validp, int *protp, target_ulong *BATu,
- target_ulong *BATl)
-{
- target_ulong bl;
- int pp, valid, prot;
-
- bl = (*BATu & BATU32_BL) << 15;
- valid = 0;
- prot = 0;
- if ((!FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000002)) ||
- (FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000001))) {
- valid = 1;
- pp = *BATl & 0x00000003;
- if (pp != 0) {
- prot = PAGE_READ | PAGE_EXEC;
- if (pp == 0x2) {
- prot |= PAGE_WRITE;
- }
- }
- }
- *blp = bl;
- *validp = valid;
- *protp = prot;
-}
-
static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, MMUAccessType access_type)
+ target_ulong eaddr, MMUAccessType access_type,
+ bool pr)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong BEPIl, BEPIu, bl;
- int i, valid, prot;
- int ret = -1;
+ int i, ret = -1;
bool ifetch = access_type == MMU_INST_FETCH;
qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
@@ -243,20 +216,19 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
BATl = &BATlt[i];
BEPIu = *BATu & BATU32_BEPIU;
BEPIl = *BATu & BATU32_BEPIL;
- bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
ifetch ? 'I' : 'D', i, eaddr, *BATu, *BATl);
- if ((eaddr & BATU32_BEPIU) == BEPIu &&
- ((eaddr & BATU32_BEPIL) & ~bl) == BEPIl) {
- /* BAT matches */
- if (valid != 0) {
+ bl = (*BATu & BATU32_BL) << 15;
+ if ((!pr && (*BATu & BATU32_VS)) || (pr && (*BATu & BATU32_VP))) {
+ if ((eaddr & BATU32_BEPIU) == BEPIu &&
+ ((eaddr & BATU32_BEPIL) & ~bl) == BEPIl) {
/* Get physical address */
ctx->raddr = (*BATl & BATU32_BEPIU) |
((eaddr & BATU32_BEPIL & bl) | (*BATl & BATU32_BEPIL)) |
(eaddr & 0x0001F000);
/* Compute access rights */
- ctx->prot = prot;
+ ctx->prot = ppc_hash32_bat_prot(*BATu, *BATl);
if (check_prot_access_type(ctx->prot, access_type)) {
qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_FMT_plx
" prot=%c%c\n", i, ctx->raddr,
@@ -300,16 +272,16 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
PowerPCCPU *cpu = env_archcpu(env);
hwaddr hash;
target_ulong vsid, sr, pgidx, ptem;
- bool key, pr, ds, nx;
+ bool key, ds, nx;
+ bool pr = FIELD_EX64(env->msr, MSR, PR);
/* First try to find a BAT entry if there are any */
- if (env->nb_BATs && get_bat_6xx_tlb(env, ctx, eaddr, access_type) == 0) {
+ if (env->nb_BATs &&
+ get_bat_6xx_tlb(env, ctx, eaddr, access_type, pr) == 0) {
return 0;
}
/* Perform segment based translation when no BATs matched */
- pr = FIELD_EX64(env->msr, MSR, PR);
-
sr = env->sr[eaddr >> 28];
key = ppc_hash32_key(pr, sr);
*keyp = key;
--
2.45.2
next prev parent reply other threads:[~2024-07-26 0:05 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-25 23:52 [PULL 00/96] ppc-for-9.1-2 queue Nicholas Piggin
2024-07-25 23:52 ` [PULL 01/96] tests/tcg: Skip failing ppc64 multi-threaded tests Nicholas Piggin
2024-07-25 23:52 ` [PULL 02/96] spapr: Migrate ail-mode-3 spapr cap Nicholas Piggin
2024-08-27 20:51 ` Michael Tokarev
2024-07-25 23:52 ` [PULL 03/96] spapr: Free stdout path Nicholas Piggin
2024-07-25 23:52 ` [PULL 04/96] ppc/vof: Fix unaligned FDT property access Nicholas Piggin
2024-07-25 23:52 ` [PULL 05/96] accel/kvm: Introduce kvm_create_and_park_vcpu() helper Nicholas Piggin
2024-07-25 23:52 ` [PULL 06/96] cpu-common.c: export cpu_get_free_index to be reused later Nicholas Piggin
2024-07-25 23:52 ` [PULL 07/96] target/ppc: handle vcpu hotplug failure gracefully Nicholas Piggin
2024-07-25 23:52 ` [PULL 08/96] target/ppc/arch_dump: set prstatus pid to cpuid Nicholas Piggin
2024-07-25 23:52 ` [PULL 09/96] linux-header: PPC: KVM: Update one-reg ids for DEXCR, HASHKEYR and HASHPKEYR Nicholas Piggin
2024-07-25 23:52 ` [PULL 10/96] target/ppc/cpu_init: Synchronize DEXCR with KVM for migration Nicholas Piggin
2024-07-25 23:52 ` [PULL 11/96] target/ppc/cpu_init: Synchronize HASHKEYR " Nicholas Piggin
2024-07-25 23:52 ` [PULL 12/96] target/ppc/cpu_init: Synchronize HASHPKEYR " Nicholas Piggin
2024-07-25 23:52 ` [PULL 13/96] ppc/pnv: Update Power10's cfam id to use Power10 DD2 Nicholas Piggin
2024-07-25 23:52 ` [PULL 14/96] ppc/pnv: Fix loss of LPC SERIRQ interrupts Nicholas Piggin
2024-07-25 23:52 ` [PULL 15/96] ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear function Nicholas Piggin
2024-07-29 10:10 ` Cédric Le Goater
2024-11-05 17:35 ` Peter Maydell
2024-11-07 14:18 ` Peter Maydell
2024-11-08 2:18 ` Nicholas Piggin
2024-07-25 23:52 ` [PULL 16/96] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10 Nicholas Piggin
2024-07-25 23:52 ` [PULL 17/96] ppc/pnv: Implement ADU access to LPC space Nicholas Piggin
2024-07-29 10:24 ` Cédric Le Goater
2024-07-25 23:52 ` [PULL 18/96] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-25 23:52 ` [PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-25 23:52 ` [PULL 20/96] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-25 23:52 ` [PULL 21/96] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-25 23:52 ` [PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines Nicholas Piggin
2024-07-25 23:52 ` [PULL 23/96] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-25 23:52 ` [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-25 23:52 ` [PULL 25/96] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-25 23:52 ` [PULL 26/96] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-25 23:53 ` [PULL 27/96] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-25 23:53 ` [PULL 28/96] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-25 23:53 ` [PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-25 23:53 ` [PULL 30/96] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-25 23:53 ` [PULL 31/96] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-25 23:53 ` [PULL 32/96] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-25 23:53 ` [PULL 33/96] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-25 23:53 ` [PULL 34/96] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-25 23:53 ` [PULL 35/96] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-25 23:53 ` [PULL 36/96] ppc/pnv: Remove ppc target dependency from pnv_xscom.h Nicholas Piggin
2024-07-25 23:53 ` [PULL 37/96] hw/ssi: Add SPI model Nicholas Piggin
2024-07-25 23:53 ` [PULL 38/96] hw/ssi: Extend " Nicholas Piggin
2024-07-29 10:32 ` Cédric Le Goater
2024-07-29 13:16 ` Peter Maydell
2024-07-29 16:39 ` Chalapathi V
2024-07-29 12:08 ` Cédric Le Goater
2024-07-29 16:23 ` Chalapathi V
2024-07-25 23:53 ` [PULL 39/96] hw/block: Add Microchip's 25CSM04 to m25p80 Nicholas Piggin
2024-07-25 23:53 ` [PULL 40/96] hw/ppc: SPI controller wiring to P10 chip Nicholas Piggin
2024-07-25 23:53 ` [PULL 41/96] tests/qtest: Add pnv-spi-seeprom qtest Nicholas Piggin
2024-07-25 23:53 ` [PULL 42/96] pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support Nicholas Piggin
2024-07-25 23:53 ` [PULL 43/96] pnv/xive2: Structure/define alignment changes Nicholas Piggin
2024-07-25 23:53 ` [PULL 44/96] pnv/xive: Support cache flush and queue sync inject with notifications Nicholas Piggin
2024-07-25 23:53 ` [PULL 45/96] pnv/xive2: Add NVG and NVC to cache watch facility Nicholas Piggin
2024-07-25 23:53 ` [PULL 46/96] pnv/xive2: Configure Virtualization Structure Tables through the PC Nicholas Piggin
2024-07-25 23:53 ` [PULL 47/96] pnv/xive2: Enable VST NVG and NVC index compression Nicholas Piggin
2024-07-25 23:53 ` [PULL 48/96] pnv/xive2: Set Translation Table for the NVC port space Nicholas Piggin
2024-07-25 23:53 ` [PULL 49/96] pnv/xive2: Fail VST entry address computation if table has no VSD Nicholas Piggin
2024-07-25 23:53 ` [PULL 50/96] pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c Nicholas Piggin
2024-07-25 23:53 ` [PULL 51/96] pnv/xive2: Refine TIMA 'info pic' output Nicholas Piggin
2024-07-25 23:53 ` [PULL 52/96] pnv/xive2: Dump more END state with 'info pic' Nicholas Piggin
2024-07-25 23:53 ` [PULL 53/96] target/ppc: Move VMX integer add/sub saturate insns to decodetree Nicholas Piggin
2024-07-25 23:53 ` [PULL 54/96] target/ppc: Improve VMX integer add/sub saturate instructions Nicholas Piggin
2024-07-25 23:53 ` [PULL 55/96] target/ppc: Move ISA300 flag check out of do_helper_XX3 Nicholas Piggin
2024-07-25 23:53 ` [PULL 56/96] target/ppc: Move VSX arithmetic and max/min insns to decodetree Nicholas Piggin
2024-07-25 23:53 ` [PULL 57/96] target/ppc: Move VSX logical instructions " Nicholas Piggin
2024-07-25 23:53 ` [PULL 58/96] target/ppc: Moving VSX scalar storage access insns " Nicholas Piggin
2024-07-25 23:53 ` [PULL 59/96] target/ppc: Move VSX vector with length " Nicholas Piggin
2024-07-25 23:53 ` [PULL 60/96] target/ppc: Move VSX vector " Nicholas Piggin
2024-07-25 23:53 ` [PULL 61/96] target/ppc: Move VSX fp compare " Nicholas Piggin
2024-07-25 23:53 ` [PULL 62/96] target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc Nicholas Piggin
2024-07-25 23:53 ` [PULL 63/96] target/ppc: Update VMX storage access insns to use tcg_gen_qemu_ld/st_i128 Nicholas Piggin
2024-07-25 23:53 ` [PULL 64/96] target/ppc : Update VSX storage access insns to use tcg_gen_qemu _ld/st_i128 Nicholas Piggin
2024-07-25 23:53 ` [PULL 65/96] target/ppc: Reorganise and rename ppc_hash32_pp_prot() Nicholas Piggin
2024-07-25 23:53 ` [PULL 66/96] target/ppc/mmu_common.c: Remove local name for a constant Nicholas Piggin
2024-07-25 23:53 ` [PULL 67/96] target/ppc/mmu_common.c: Remove single use local variable Nicholas Piggin
2024-07-25 23:53 ` [PULL 68/96] " Nicholas Piggin
2024-07-25 23:53 ` [PULL 69/96] target/ppc/mmu_common.c: Remove another " Nicholas Piggin
2024-07-25 23:53 ` [PULL 70/96] target/ppc/mmu_common.c: Remove yet " Nicholas Piggin
2024-07-25 23:53 ` [PULL 71/96] target/ppc/mmu_common.c: Return directly in ppc6xx_tlb_pte_check() Nicholas Piggin
2024-07-25 23:53 ` [PULL 72/96] target/ppc/mmu_common.c: Simplify ppc6xx_tlb_pte_check() Nicholas Piggin
2024-07-25 23:53 ` [PULL 73/96] target/ppc/mmu_common.c: Remove unused field from mmu_ctx_t Nicholas Piggin
2024-07-25 23:53 ` [PULL 74/96] target/ppc/mmu_common.c: Remove hash " Nicholas Piggin
2024-07-25 23:53 ` [PULL 75/96] target/ppc/mmu_common.c: Remove pte_update_flags() Nicholas Piggin
2024-07-25 23:53 ` [PULL 76/96] target/ppc/mmu_common.c: Remove nx field from mmu_ctx_t Nicholas Piggin
2024-07-25 23:53 ` [PULL 77/96] target/ppc/mmu_common.c: Convert local variable to bool Nicholas Piggin
2024-07-25 23:53 ` [PULL 78/96] target/ppc/mmu_common.c: Remove single use local variable Nicholas Piggin
2024-07-25 23:53 ` [PULL 79/96] target/ppc/mmu_common.c: Simplify a switch statement Nicholas Piggin
2024-07-25 23:53 ` [PULL 80/96] target/ppc/mmu_common.c: Inline and remove ppc6xx_tlb_pte_check() Nicholas Piggin
2024-07-25 23:53 ` [PULL 81/96] target/ppc/mmu_common.c: Remove ptem field from mmu_ctx_t Nicholas Piggin
2024-07-25 23:53 ` [PULL 82/96] target/ppc: Add function to get protection key for hash32 MMU Nicholas Piggin
2024-07-25 23:53 ` [PULL 83/96] target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_prot() Nicholas Piggin
2024-07-25 23:53 ` [PULL 84/96] target/ppc/mmu_common.c: Init variable in function that relies on it Nicholas Piggin
2024-07-25 23:53 ` [PULL 85/96] target/ppc/mmu_common.c: Remove key field from mmu_ctx_t Nicholas Piggin
2024-07-25 23:53 ` [PULL 86/96] target/ppc/mmu_common.c: Stop using ctx in ppc6xx_tlb_check() Nicholas Piggin
2024-07-25 23:54 ` [PULL 87/96] target/ppc/mmu_common.c: Rename function parameter Nicholas Piggin
2024-07-25 23:54 ` [PULL 88/96] target/ppc/mmu_common.c: Use defines instead of numeric constants Nicholas Piggin
2024-07-25 23:54 ` Nicholas Piggin [this message]
2024-07-25 23:54 ` [PULL 90/96] target/ppc/mmu_common.c: Stop using ctx in get_bat_6xx_tlb() Nicholas Piggin
2024-07-25 23:54 ` [PULL 91/96] target/ppc/mmu_common.c: Remove mmu_ctx_t Nicholas Piggin
2024-07-25 23:54 ` [PULL 92/96] target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_raddr() Nicholas Piggin
2024-07-25 23:54 ` [PULL 93/96] target/ppc/mmu-hash32.c: Move get_pteg_offset32() to the header Nicholas Piggin
2024-07-25 23:54 ` [PULL 94/96] target/ppc: Unexport some functions from mmu-book3s-v3.h Nicholas Piggin
2024-07-25 23:54 ` [PULL 95/96] target/ppc/mmu-radix64: Remove externally unused parts from header Nicholas Piggin
2024-07-25 23:54 ` [PULL 96/96] target/ppc: Remove includes from mmu-book3s-v3.h Nicholas Piggin
2024-07-27 6:57 ` [PULL 00/96] ppc-for-9.1-2 queue Richard Henderson
2024-07-29 9:43 ` Philippe Mathieu-Daudé
2024-07-31 7:12 ` Nicholas Piggin
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