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From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, jim.shu@sifive.com,
	andy.chiu@sifive.com, jesse.huang@sifive.com,
	kito.cheng@sifive.com
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu,
	bmeng.cn@gmail.com, liwei1518@gmail.com,
	dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
	Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v2 14/24] target/riscv: compressed encodings for sspush and sspopchk
Date: Mon, 29 Jul 2024 10:53:16 -0700	[thread overview]
Message-ID: <20240729175327.73705-15-debug@rivosinc.com> (raw)
In-Reply-To: <20240729175327.73705-1-debug@rivosinc.com>

sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.

Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
---
 target/riscv/insn16.decode | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 3953bcf82d..d9fb74fef6 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -69,10 +69,12 @@
 # Formats 16:
 @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
 @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
+@c_sspop   ... . ..... .....  .. &i      imm=0      rs1=5     rd=0
 @cl_q      ... . .....  ..... .. &i      imm=%uimm_cl_q   rs1=%rs1_3  rd=%rs2_3
 @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
 @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
 @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
+@c_sspush  ... ... ... .. ... .. &s      imm=0 rs1=0 rs2=1
 @cs_q      ... ... ... .. ... .. &s      imm=%uimm_cl_q   rs1=%rs1_3  rs2=%rs2_3
 @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
 @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
@@ -140,6 +142,8 @@ sw                110  ... ... .. ... 00 @cs_w
 addi              000 .  .....  ..... 01 @ci
 addi              010 .  .....  ..... 01 @c_li
 {
+  sspush          011 0  00001  00000 01 @c_sspush # c.sspush x1 carving out of zcmops
+  sspopchk        011 0  00101  00000 01 @c_sspop # c.sspopchk x5 carving out of zcmops
   c_mop_n         011 0 0 n:3 1 00000 01
   illegal         011 0  -----  00000 01 # c.addi16sp and c.lui, RES nzimm=0
   addi            011 .  00010  ..... 01 @c_addi16sp
-- 
2.44.0



  parent reply	other threads:[~2024-07-29 17:54 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-29 17:53 [PATCH v2 00/24] riscv support for control flow integrity extensions Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 01/24] target/riscv: Add zicfilp extension Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 02/24] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 03/24] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-07-29 23:04   ` Richard Henderson
2024-07-29 23:33     ` Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 04/24] target/riscv: additional code information for sw check Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 05/24] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-07-29 23:15   ` Richard Henderson
2024-08-01  6:59     ` Deepak Gupta
2024-08-01  9:12       ` Richard Henderson
2024-08-01 17:05         ` Deepak Gupta
2024-08-01 21:34           ` Richard Henderson
2024-07-29 17:53 ` [PATCH v2 06/24] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 07/24] disas/riscv: enabled `lpad` disassembly Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 08/24] linux-user/syscall: introduce prctl for indirect branch tracking Deepak Gupta
2024-07-30  6:21   ` Richard Henderson
2024-07-29 17:53 ` [PATCH v2 09/24] linux-user/riscv: implement indirect branch tracking prctls Deepak Gupta
2024-07-30  6:26   ` Richard Henderson
2024-08-01  7:02     ` Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 10/24] target/riscv: Add zicfiss extension Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 11/24] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 12/24] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 13/24] target/riscv: implement zicfiss instructions Deepak Gupta
2024-07-29 17:53 ` Deepak Gupta [this message]
2024-07-29 17:53 ` [PATCH v2 15/24] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 16/24] target/riscv: shadow stack mmu index for shadow stack instructions Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 17/24] linux-user/syscall: introduce prctl for shadow stack enable/disable Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 18/24] linux-user/riscv: setup/teardown zicfiss shadow stack for qemu-user Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 19/24] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 20/24] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 21/24] target/riscv: add trace-hooks for each case of sw-check exception Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 22/24] linux-user: permit RISC-V CFI dynamic entry in VDSO Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 23/24] linux-user: Add RISC-V zicfilp support " Deepak Gupta
2024-07-29 17:53 ` [PATCH v2 24/24] linux-user/riscv: Adding zicfiss/lp extension in hwprobe syscall Deepak Gupta

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