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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acab4e161sm786153066b.65.2024.07.31.09.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 09:50:54 -0700 (PDT) Date: Wed, 31 Jul 2024 18:50:53 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: Jason Chien , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, frank.chang@sifive.com, tjeznach@rivosinc.com Subject: Re: [PATCH v5 11/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications Message-ID: <20240731-30c03698cd1c889a4485e2b0@orel> References: <20240708173501.426225-1-dbarboza@ventanamicro.com> <20240708173501.426225-12-dbarboza@ventanamicro.com> <8e54f48e-379b-42b8-8017-886ead154415@sifive.com> <49fe48d5-42d0-46fc-899e-50960941c3a2@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <49fe48d5-42d0-46fc-899e-50960941c3a2@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=ajones@ventanamicro.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jul 31, 2024 at 01:27:09PM GMT, Daniel Henrique Barboza wrote: > Hi Jason, > > > On 7/23/24 12:25 PM, Jason Chien wrote: > > Hi Daniel, > > > > On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote: > > > From: Andrew Jones > > > > > > And add mrif notification trace. > > > > > > Signed-off-by: Andrew Jones > > > Reviewed-by: Daniel Henrique Barboza > > > Reviewed-by: Frank Chang > > > --- > > >   hw/riscv/riscv-iommu-pci.c | 2 +- > > >   hw/riscv/riscv-iommu.c     | 1 + > > >   hw/riscv/trace-events      | 1 + > > >   3 files changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c > > > index 7b82ce0645..d7e5f20885 100644 > > > --- a/hw/riscv/riscv-iommu-pci.c > > > +++ b/hw/riscv/riscv-iommu-pci.c > > > @@ -81,7 +81,7 @@ static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) > > >       pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | > > >                        PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); > > > -    int ret = msix_init(dev, RISCV_IOMMU_INTR_COUNT, > > > +    int ret = msix_init(dev, RISCV_IOMMU_INTR_COUNT + 1, > > The new interrupt is not marked as used with msix_vector_use(). > > I took at look at what this patch is actually doing and, at least in the MRIF setup > I have, it's not doing much because we're not hitting the MRIF path inside the > emulation. So we're not hitting the trace and this extra MSI isn't being used. > > Drew is taking a look into it in the kernel side. Until we get a better idea on what's > happening I'll remove this patch from the series. We can re-introduce it again later > in this series or in the follow-up. I recommend adding the trace to whatever patch introduces the MRIF path in this series since we'll want the trace for testing regardless. If we need another fix to this series for MRIFs then I'll post that separately on top. Thanks, drew