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Tsirkin" To: BALATON Zoltan Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , qemu-devel@nongnu.org, Aurelien Jarno Subject: Re: [PATCH-for-9.1 v3 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Message-ID: <20240801113646-mutt-send-email-mst@kernel.org> References: <20240801150021.52977-1-philmd@linaro.org> <20240801150021.52977-2-philmd@linaro.org> <5e765e4d-5314-0737-fccf-635d9365f796@eik.bme.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <5e765e4d-5314-0737-fccf-635d9365f796@eik.bme.hu> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.131, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 01, 2024 at 05:30:38PM +0200, BALATON Zoltan wrote: > On Thu, 1 Aug 2024, Philippe Mathieu-Daudé wrote: > > Reset config values in the device RESET phase, not only once > > when the device is realized, because otherwise the device can > > use unknown values at reset. > > > > Mention the datasheet referenced. Remove the "Malta assumptions > > ahead" comment since the reset values from the datasheet are used. > > > > Reported-by: Michael S. Tsirkin > > Signed-off-by: Philippe Mathieu-Daudé > > --- > > hw/pci-host/gt64120.c | 14 +++++++++++--- > > 1 file changed, 11 insertions(+), 3 deletions(-) > > > > diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c > > index e02efc9e2e..b68d647753 100644 > > --- a/hw/pci-host/gt64120.c > > +++ b/hw/pci-host/gt64120.c > > @@ -1,6 +1,8 @@ > > /* > > * QEMU GT64120 PCI host > > * > > + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) > > + * > > * Copyright (c) 2006,2007 Aurelien Jarno > > * > > * Permission is hereby granted, free of charge, to any person obtaining a copy > > @@ -1211,19 +1213,24 @@ static void gt64120_realize(DeviceState *dev, Error **errp) > > empty_slot_init("GT64120", 0, 0x20000000); > > } > > > > -static void gt64120_pci_realize(PCIDevice *d, Error **errp) > > +static void gt64120_pci_reset_hold(Object *obj, ResetType type) > > { > > - /* FIXME: Malta specific hw assumptions ahead */ > > + PCIDevice *d = PCI_DEVICE(obj); > > + > > + /* Values from chapter 17.16 "PCI Configuration" */ > > + > > pci_set_word(d->config + PCI_COMMAND, 0); > > pci_set_word(d->config + PCI_STATUS, > > PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); > > pci_config_set_prog_interface(d->config, 0); > > + > > pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); > > pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); > > pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); > > pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); > > pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); > > pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); > > + > > pci_set_byte(d->config + 0x3d, 0x01); > > } > > > > @@ -1231,8 +1238,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) > > { > > PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); > > DeviceClass *dc = DEVICE_CLASS(klass); > > + ResettableClass *rc = RESETTABLE_CLASS(klass); > > > > - k->realize = gt64120_pci_realize; > > + rc->phases.hold = gt64120_pci_reset_hold; > > Why reset_hold and not a simple reset method which is more usual? Good point. And I'd keep it limited, e.g. wmask can be set once, no need to tweak it on reset. > If > there's an explanation maybe it could be mentioned in the commit message. > Other than that this should work so you can add: > > Reviewed-by: BALATON Zoltan > > if that helps but I don't know much about this chip (even if it's similar to > mv6436x). > > Regards, > BALATON Zoltan > > > k->vendor_id = PCI_VENDOR_ID_MARVELL; > > k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; > > k->revision = 0x10; > >