From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Aurelien Jarno" <aurelien@aurel32.net>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
"BALATON Zoltan" <balaton@eik.bme.hu>
Subject: [PATCH-for-9.1 v3 0/2] hw/pci-host/gt64120: Set PCI base address register write mask
Date: Thu, 1 Aug 2024 17:00:19 +0200 [thread overview]
Message-ID: <20240801150021.52977-1-philmd@linaro.org> (raw)
v3: Move comment from patch 2 to 1
v2: Move reset values from Realize to ResetHold (mst)
Philippe Mathieu-Daudé (2):
hw/pci-host/gt64120: Reset config registers during RESET phase
hw/pci-host/gt64120: Set PCI base address register write mask
hw/pci-host/gt64120.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
--
2.45.2
next reply other threads:[~2024-08-01 15:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-01 15:00 Philippe Mathieu-Daudé [this message]
2024-08-01 15:00 ` [PATCH-for-9.1 v3 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé
2024-08-01 15:30 ` BALATON Zoltan
2024-08-01 15:37 ` Michael S. Tsirkin
2024-08-01 17:03 ` Philippe Mathieu-Daudé
2024-08-01 17:13 ` Peter Maydell
2024-08-02 17:01 ` Philippe Mathieu-Daudé
2024-08-01 15:00 ` [PATCH-for-9.1 v3 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé
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