From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Warner Losh <imp@bsdimp.com>, Ajeet Singh <itachis@FreeBSD.org>
Subject: [PATCH 00/18] bsd-user: Comprehensive RISCV support
Date: Fri, 2 Aug 2024 18:34:05 +1000 [thread overview]
Message-ID: <20240802083423.142365-1-itachis@FreeBSD.org> (raw)
This patch series provides support for the RISC-V 64-bit architecture,
enabling signal processing, system call handling, threading, and memory
management tailored to RISC-V.
Mark Corbin (16):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V CPU register cloning and reset functions
bsd-user: Implement RISC-V TLS register setup
bsd-user: Add prototype for RISC-V TLS register setup
bsd-user: Add RISC-V ELF definitions and hardware capability detection
bsd-user: Define RISC-V register structures and register copying
bsd-user: Add RISC-V signal trampoline setup function
bsd-user: Implement RISC-V sysarch system call emulation
bsd-user: Add RISC-V thread setup and initialization support
bsd-user: Define RISC-V VM parameters and helper functions
bsd-user: Define RISC-V system call structures and constants
bsd-user: Define RISC-V signal handling structures and constants
bsd-user: Implement RISC-V signal trampoline setup functions
bsd-user: Implement 'get_mcontext' for RISC-V
bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
Warner Losh (2):
bsd-user: Add generic RISC-V64 target definitions
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++
bsd-user/riscv/target.h | 20 +++
bsd-user/riscv/target_arch.h | 27 ++++
bsd-user/riscv/target_arch_cpu.c | 29 +++++
bsd-user/riscv/target_arch_cpu.h | 147 ++++++++++++++++++++++
bsd-user/riscv/target_arch_elf.h | 48 ++++++++
bsd-user/riscv/target_arch_reg.h | 88 +++++++++++++
bsd-user/riscv/target_arch_signal.h | 75 ++++++++++++
bsd-user/riscv/target_arch_sigtramp.h | 46 +++++++
bsd-user/riscv/target_arch_sysarch.h | 41 +++++++
bsd-user/riscv/target_arch_thread.h | 47 +++++++
bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++
bsd-user/riscv/target_syscall.h | 38 ++++++
configs/targets/riscv64-bsd-user.mak | 4 +
14 files changed, 833 insertions(+)
create mode 100644 bsd-user/riscv/signal.c
create mode 100644 bsd-user/riscv/target.h
create mode 100644 bsd-user/riscv/target_arch.h
create mode 100644 bsd-user/riscv/target_arch_cpu.c
create mode 100644 bsd-user/riscv/target_arch_cpu.h
create mode 100644 bsd-user/riscv/target_arch_elf.h
create mode 100644 bsd-user/riscv/target_arch_reg.h
create mode 100644 bsd-user/riscv/target_arch_signal.h
create mode 100644 bsd-user/riscv/target_arch_sigtramp.h
create mode 100644 bsd-user/riscv/target_arch_sysarch.h
create mode 100644 bsd-user/riscv/target_arch_thread.h
create mode 100644 bsd-user/riscv/target_arch_vmparam.h
create mode 100644 bsd-user/riscv/target_syscall.h
create mode 100644 configs/targets/riscv64-bsd-user.mak
--
2.34.1
next reply other threads:[~2024-08-02 8:36 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 8:34 Ajeet Singh [this message]
2024-08-02 8:34 ` [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-02 12:41 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-02 12:54 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-02 12:58 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-02 13:01 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 05/18] bsd-user: Add prototype for " Ajeet Singh
2024-08-02 13:04 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-02 13:13 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-02 13:20 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-02 13:24 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 09/18] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-02 13:27 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-02 13:30 ` Richard Henderson
2024-08-03 0:05 ` Warner Losh
2024-08-02 8:34 ` [PATCH 11/18] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-02 13:33 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 12/18] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-02 13:35 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 13/18] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-02 13:35 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 14/18] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-02 13:38 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 15/18] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-02 13:46 ` Richard Henderson
2024-08-03 0:04 ` Warner Losh
2024-08-03 9:33 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 16/18] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-02 13:47 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 17/18] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-02 13:48 ` Richard Henderson
2024-08-02 8:34 ` [PATCH 18/18] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-08-02 13:50 ` Richard Henderson
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