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From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Warner Losh <imp@bsdimp.com>,
	Mark Corbin <mark.corbin@embecsom.com>,
	Ajeet Singh <itachis@FreeBSD.org>
Subject: [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function
Date: Fri,  2 Aug 2024 18:34:13 +1000	[thread overview]
Message-ID: <20240802083423.142365-9-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240802083423.142365-1-itachis@FreeBSD.org>

From: Mark Corbin <mark.corbin@embecsom.com>

Implemented the `setup_sigtramp` function for setting up the signal
trampoline code in the RISC-V architecture.

Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
 bsd-user/riscv/target_arch_sigtramp.h | 46 +++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 bsd-user/riscv/target_arch_sigtramp.h

diff --git a/bsd-user/riscv/target_arch_sigtramp.h b/bsd-user/riscv/target_arch_sigtramp.h
new file mode 100644
index 0000000000..39c878db22
--- /dev/null
+++ b/bsd-user/riscv/target_arch_sigtramp.h
@@ -0,0 +1,46 @@
+/*
+ * RISC-V sigcode
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGTRAMP_H
+#define TARGET_ARCH_SIGTRAMP_H
+
+/* Compare with sigcode() in riscv/riscv/locore.S */
+static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc,
+        unsigned sys_sigreturn)
+{
+    int i;
+    uint32_t sys_exit = TARGET_FREEBSD_NR_exit;
+
+    uint32_t sigtramp_code[] = {
+    /* 1 */ 0x00010513,                         /* mv a0, sp */
+    /* 2 */ 0x00050513 + (sigf_uc << 20),       /* addi a0, a0, sigf_uc */
+    /* 3 */ 0x00000293 + (sys_sigreturn << 20), /* li t0, sys_sigreturn */
+    /* 4 */ 0x00000073,                         /* ecall */
+    /* 5 */ 0x00000293 + (sys_exit << 20),      /* li t0, sys_exit */
+    /* 6 */ 0x00000073,                         /* ecall */
+    /* 7 */ 0xFF1FF06F                          /* b -16 */
+    };
+
+    for (i = 0; i < 7; i++) {
+        tswap32s(&sigtramp_code[i]);
+    }
+
+    return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE);
+}
+#endif /* TARGET_ARCH_SIGTRAMP_H */
-- 
2.34.1



  parent reply	other threads:[~2024-08-02  8:37 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-02  8:34 [PATCH 00/18] bsd-user: Comprehensive RISCV support Ajeet Singh
2024-08-02  8:34 ` [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-02 12:41   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-02 12:54   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-02 12:58   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-02 13:01   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 05/18] bsd-user: Add prototype for " Ajeet Singh
2024-08-02 13:04   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-02 13:13   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-02 13:20   ` Richard Henderson
2024-08-02  8:34 ` Ajeet Singh [this message]
2024-08-02 13:24   ` [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function Richard Henderson
2024-08-02  8:34 ` [PATCH 09/18] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-02 13:27   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-02 13:30   ` Richard Henderson
2024-08-03  0:05     ` Warner Losh
2024-08-02  8:34 ` [PATCH 11/18] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-02 13:33   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 12/18] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-02 13:35   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 13/18] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-02 13:35   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 14/18] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-02 13:38   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 15/18] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-02 13:46   ` Richard Henderson
2024-08-03  0:04     ` Warner Losh
2024-08-03  9:33       ` Richard Henderson
2024-08-02  8:34 ` [PATCH 16/18] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-02 13:47   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 17/18] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-02 13:48   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 18/18] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-08-02 13:50   ` Richard Henderson

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