* [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-07 7:14 ` maobibo
2024-08-06 12:51 ` [PULL 02/28] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() Philippe Mathieu-Daudé
` (27 subsequent siblings)
28 siblings, 1 reply; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-2-philmd@linaro.org>
---
include/hw/intc/loongson_ipi.h | 6 +++---
hw/intc/loongson_ipi.c | 16 ++++++++--------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 3f795edbf3..efb772f384 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -31,10 +31,10 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
+OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
typedef struct IPICore {
- LoongsonIPI *ipi;
+ LoongsonIPIState *ipi;
MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
@@ -45,7 +45,7 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
-struct LoongsonIPI {
+struct LoongsonIPIState {
SysBusDevice parent_obj;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 682cec96f3..903483ae80 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
- LoongsonIPI *ipi = opaque;
+ LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
- LoongsonIPI *ipi = s->ipi;
+ LoongsonIPIState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
- LoongsonIPI *ipi = opaque;
+ LoongsonIPIState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
- LoongsonIPI *s = LOONGSON_IPI(dev);
+ LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -320,7 +320,7 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
static void loongson_ipi_unrealize(DeviceState *dev)
{
- LoongsonIPI *s = LOONGSON_IPI(dev);
+ LoongsonIPIState *s = LOONGSON_IPI(dev);
g_free(s->cpu);
}
@@ -344,14 +344,14 @@ static const VMStateDescription vmstate_loongson_ipi = {
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu,
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu,
vmstate_ipi_core, IPICore),
VMSTATE_END_OF_LIST()
}
};
static Property ipi_properties[] = {
- DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1),
+ DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -369,7 +369,7 @@ static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(LoongsonIPI),
+ .instance_size = sizeof(LoongsonIPIState),
.class_init = loongson_ipi_class_init,
}
};
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState
2024-08-06 12:51 ` [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState Philippe Mathieu-Daudé
@ 2024-08-07 7:14 ` maobibo
2024-08-07 7:24 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 33+ messages in thread
From: maobibo @ 2024-08-07 7:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Song Gao, Richard Henderson, Jiaxun Yang
Philippe,
I checkout the latest code, it works well.
Thanks for your efforts.
Regards
Bibo Mao
On 2024/8/6 下午8:51, Philippe Mathieu-Daudé wrote:
> From: Bibo Mao <maobibo@loongson.cn>
>
> We'll have to add LoongsonIPIClass in few commits,
> so rename LoongsonIPI as LoongsonIPIState for clarity.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> [PMD: Extracted from bigger commit, added commit description]
> Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
> Tested-by: Bibo Mao <maobibo@loongson.cn>
> Acked-by: Song Gao <gaosong@loongson.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Message-Id: <20240805180622.21001-2-philmd@linaro.org>
> ---
> include/hw/intc/loongson_ipi.h | 6 +++---
> hw/intc/loongson_ipi.c | 16 ++++++++--------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
> index 3f795edbf3..efb772f384 100644
> --- a/include/hw/intc/loongson_ipi.h
> +++ b/include/hw/intc/loongson_ipi.h
> @@ -31,10 +31,10 @@
> #define IPI_MBX_NUM 4
>
> #define TYPE_LOONGSON_IPI "loongson_ipi"
> -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
> +OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
>
> typedef struct IPICore {
> - LoongsonIPI *ipi;
> + LoongsonIPIState *ipi;
> MemoryRegion *ipi_mmio_mem;
> uint32_t status;
> uint32_t en;
> @@ -45,7 +45,7 @@ typedef struct IPICore {
> qemu_irq irq;
> } IPICore;
>
> -struct LoongsonIPI {
> +struct LoongsonIPIState {
> SysBusDevice parent_obj;
> MemoryRegion ipi_iocsr_mem;
> MemoryRegion ipi64_iocsr_mem;
> diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
> index 682cec96f3..903483ae80 100644
> --- a/hw/intc/loongson_ipi.c
> +++ b/hw/intc/loongson_ipi.c
> @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
> uint64_t *data,
> unsigned size, MemTxAttrs attrs)
> {
> - LoongsonIPI *ipi = opaque;
> + LoongsonIPIState *ipi = opaque;
> IPICore *s;
>
> if (attrs.requester_id >= ipi->num_cpu) {
> @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
> MemTxAttrs attrs)
> {
> IPICore *s = opaque;
> - LoongsonIPI *ipi = s->ipi;
> + LoongsonIPIState *ipi = s->ipi;
> int index = 0;
> uint32_t cpuid;
> uint8_t vector;
> @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
> uint64_t val, unsigned size,
> MemTxAttrs attrs)
> {
> - LoongsonIPI *ipi = opaque;
> + LoongsonIPIState *ipi = opaque;
> IPICore *s;
>
> if (attrs.requester_id >= ipi->num_cpu) {
> @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
>
> static void loongson_ipi_realize(DeviceState *dev, Error **errp)
> {
> - LoongsonIPI *s = LOONGSON_IPI(dev);
> + LoongsonIPIState *s = LOONGSON_IPI(dev);
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> int i;
>
> @@ -320,7 +320,7 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
>
> static void loongson_ipi_unrealize(DeviceState *dev)
> {
> - LoongsonIPI *s = LOONGSON_IPI(dev);
> + LoongsonIPIState *s = LOONGSON_IPI(dev);
>
> g_free(s->cpu);
> }
> @@ -344,14 +344,14 @@ static const VMStateDescription vmstate_loongson_ipi = {
> .version_id = 2,
> .minimum_version_id = 2,
> .fields = (const VMStateField[]) {
> - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu,
> + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu,
> vmstate_ipi_core, IPICore),
> VMSTATE_END_OF_LIST()
> }
> };
>
> static Property ipi_properties[] = {
> - DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1),
> + DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -369,7 +369,7 @@ static const TypeInfo loongson_ipi_types[] = {
> {
> .name = TYPE_LOONGSON_IPI,
> .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(LoongsonIPI),
> + .instance_size = sizeof(LoongsonIPIState),
> .class_init = loongson_ipi_class_init,
> }
> };
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState
2024-08-07 7:14 ` maobibo
@ 2024-08-07 7:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-07 7:24 UTC (permalink / raw)
To: maobibo, qemu-devel; +Cc: Song Gao, Richard Henderson, Jiaxun Yang
On 7/8/24 09:14, maobibo wrote:
> Philippe,
>
> I checkout the latest code, it works well.
> Thanks for your efforts.
Thanks! It took quite some time, but in the end I
believe the commit will be easier to review / bisect
in case of problem.
>
> Regards
> Bibo Mao
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PULL 02/28] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 03/28] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub Philippe Mathieu-Daudé
` (26 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-3-philmd@linaro.org>
---
hw/intc/loongson_ipi.c | 40 ++++++++++++++++++++++++++++------------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 903483ae80..8aab7e48e8 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -301,30 +301,46 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
s->cpu = g_new0(IPICore, s->num_cpu);
- if (s->cpu == NULL) {
- error_setg(errp, "Memory allocation for IPICore faile");
- return;
- }
-
for (i = 0; i < s->num_cpu; i++) {
s->cpu[i].ipi = s;
- s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
- g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
- memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
- &loongson_ipi_core_ops, &s->cpu[i], name, 0x48);
- sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
}
}
-static void loongson_ipi_unrealize(DeviceState *dev)
+static void loongson_ipi_realize(DeviceState *dev, Error **errp)
+{
+ LoongsonIPIState *s = LOONGSON_IPI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ Error *local_err = NULL;
+
+ loongson_ipi_common_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ for (unsigned i = 0; i < s->num_cpu; i++) {
+ s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
+ g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
+ memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
+ &loongson_ipi_core_ops, &s->cpu[i], name, 0x48);
+ sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
+ }
+}
+
+static void loongson_ipi_common_unrealize(DeviceState *dev)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
g_free(s->cpu);
}
+static void loongson_ipi_unrealize(DeviceState *dev)
+{
+ loongson_ipi_common_unrealize(dev);
+}
+
static const VMStateDescription vmstate_ipi_core = {
.name = "ipi-single",
.version_id = 2,
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 03/28] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 02/28] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 04/28] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h Philippe Mathieu-Daudé
` (25 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-4-philmd@linaro.org>
---
MAINTAINERS | 4 ++++
include/hw/intc/loongson_ipi.h | 14 ++++++++++++--
include/hw/intc/loongson_ipi_common.h | 26 ++++++++++++++++++++++++++
hw/intc/loongson_ipi.c | 10 +++++++---
hw/intc/loongson_ipi_common.c | 22 ++++++++++++++++++++++
hw/intc/Kconfig | 4 ++++
hw/intc/meson.build | 1 +
7 files changed, 76 insertions(+), 5 deletions(-)
create mode 100644 include/hw/intc/loongson_ipi_common.h
create mode 100644 hw/intc/loongson_ipi_common.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e34c2bd4cd..5ca701cf0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1250,8 +1250,10 @@ F: configs/devices/loongarch64-softmmu/default.mak
F: hw/loongarch/
F: include/hw/loongarch/virt.h
F: include/hw/intc/loongarch_*.h
+F: include/hw/intc/loongson_ipi_common.h
F: include/hw/intc/loongson_ipi.h
F: hw/intc/loongarch_*.c
+F: hw/intc/loongson_ipi_common.c
F: hw/intc/loongson_ipi.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
@@ -1386,11 +1388,13 @@ Loongson-3 virtual platforms
M: Huacai Chen <chenhuacai@kernel.org>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Maintained
+F: hw/intc/loongson_ipi_common.c
F: hw/intc/loongson_ipi.c
F: hw/intc/loongson_liointc.c
F: hw/mips/loongson3_bootp.c
F: hw/mips/loongson3_bootp.h
F: hw/mips/loongson3_virt.c
+F: include/hw/intc/loongson_ipi_common.h
F: include/hw/intc/loongson_ipi.h
F: include/hw/intc/loongson_liointc.h
F: tests/avocado/machine_mips_loongson3v.py
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index efb772f384..9c9030761e 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -8,6 +8,8 @@
#ifndef HW_LOONGSON_IPI_H
#define HW_LOONGSON_IPI_H
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
/* Mainy used by iocsr read and write */
@@ -31,7 +33,7 @@
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
-OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI)
+OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
@@ -45,8 +47,16 @@ typedef struct IPICore {
qemu_irq irq;
} IPICore;
+struct LoongsonIPIClass {
+ LoongsonIPICommonClass parent_class;
+
+ DeviceRealize parent_realize;
+ DeviceUnrealize parent_unrealize;
+};
+
struct LoongsonIPIState {
- SysBusDevice parent_obj;
+ LoongsonIPICommonState parent_obj;
+
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
new file mode 100644
index 0000000000..70ac69d0ba
--- /dev/null
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson ipi interrupt header files
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGSON_IPI_COMMON_H
+#define HW_LOONGSON_IPI_COMMON_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
+OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
+ LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+
+struct LoongsonIPICommonState {
+ SysBusDevice parent_obj;
+};
+
+struct LoongsonIPICommonClass {
+ SysBusDeviceClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 8aab7e48e8..7d15c28e94 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -374,9 +374,12 @@ static Property ipi_properties[] = {
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
- dc->realize = loongson_ipi_realize;
- dc->unrealize = loongson_ipi_unrealize;
+ device_class_set_parent_realize(dc, loongson_ipi_realize,
+ &lic->parent_realize);
+ device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
+ &lic->parent_unrealize);
device_class_set_props(dc, ipi_properties);
dc->vmsd = &vmstate_loongson_ipi;
}
@@ -384,8 +387,9 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
static const TypeInfo loongson_ipi_types[] = {
{
.name = TYPE_LOONGSON_IPI,
- .parent = TYPE_SYS_BUS_DEVICE,
+ .parent = TYPE_LOONGSON_IPI_COMMON,
.instance_size = sizeof(LoongsonIPIState),
+ .class_size = sizeof(LoongsonIPIClass),
.class_init = loongson_ipi_class_init,
}
};
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
new file mode 100644
index 0000000000..43002fe556
--- /dev/null
+++ b/hw/intc/loongson_ipi_common.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson IPI interrupt common support
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/intc/loongson_ipi_common.h"
+
+static const TypeInfo loongarch_ipi_common_types[] = {
+ {
+ .name = TYPE_LOONGSON_IPI_COMMON,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LoongsonIPICommonState),
+ .class_size = sizeof(LoongsonIPICommonClass),
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(loongarch_ipi_common_types)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 58b6d3a710..a2a0fdca85 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -87,8 +87,12 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+config LOONGSON_IPI_COMMON
+ bool
+
config LOONGSON_IPI
bool
+ select LOONGSON_IPI_COMMON
config LOONGARCH_PCH_PIC
bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index afd1aa51ee..a09a527207 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -69,6 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 04/28] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-08-06 12:51 ` [PULL 03/28] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 05/28] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState Philippe Mathieu-Daudé
` (24 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-5-philmd@linaro.org>
---
include/hw/intc/loongson_ipi.h | 18 ------------------
include/hw/intc/loongson_ipi_common.h | 19 +++++++++++++++++++
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 9c9030761e..70e00dc1a7 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,24 +12,6 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-/* Mainy used by iocsr read and write */
-#define SMP_IPI_MAILBOX 0x1000ULL
-#define CORE_STATUS_OFF 0x0
-#define CORE_EN_OFF 0x4
-#define CORE_SET_OFF 0x8
-#define CORE_CLEAR_OFF 0xc
-#define CORE_BUF_20 0x20
-#define CORE_BUF_28 0x28
-#define CORE_BUF_30 0x30
-#define CORE_BUF_38 0x38
-#define IOCSR_IPI_SEND 0x40
-#define IOCSR_MAIL_SEND 0x48
-#define IOCSR_ANY_SEND 0x158
-
-#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
-#define MAIL_SEND_OFFSET 0
-#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
-
#define IPI_MBX_NUM 4
#define TYPE_LOONGSON_IPI "loongson_ipi"
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index 70ac69d0ba..b43b77bda6 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -23,4 +23,23 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
};
+/* Mainy used by iocsr read and write */
+#define SMP_IPI_MAILBOX 0x1000ULL
+
+#define CORE_STATUS_OFF 0x0
+#define CORE_EN_OFF 0x4
+#define CORE_SET_OFF 0x8
+#define CORE_CLEAR_OFF 0xc
+#define CORE_BUF_20 0x20
+#define CORE_BUF_28 0x28
+#define CORE_BUF_30 0x30
+#define CORE_BUF_38 0x38
+#define IOCSR_IPI_SEND 0x40
+#define IOCSR_MAIL_SEND 0x48
+#define IOCSR_ANY_SEND 0x158
+
+#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET 0
+#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+
#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 05/28] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-08-06 12:51 ` [PULL 04/28] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 06/28] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h Philippe Mathieu-Daudé
` (23 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
It is easier to manage one array of MMIO MR rather
than one per vCPU.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-6-philmd@linaro.org>
---
include/hw/intc/loongson_ipi.h | 2 +-
hw/intc/loongson_ipi.c | 10 +++++++---
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 70e00dc1a7..5a52dfbf4d 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPIState *ipi;
- MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
uint32_t set;
@@ -39,6 +38,7 @@ struct LoongsonIPIClass {
struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
+ MemoryRegion *ipi_mmio_mem;
MemoryRegion ipi_iocsr_mem;
MemoryRegion ipi64_iocsr_mem;
uint32_t num_cpu;
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 7d15c28e94..03878b896f 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
return;
}
+ s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
for (unsigned i = 0; i < s->num_cpu; i++) {
- s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
- memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
+ memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev),
&loongson_ipi_core_ops, &s->cpu[i], name, 0x48);
- sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
+ sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]);
}
}
@@ -338,6 +338,10 @@ static void loongson_ipi_common_unrealize(DeviceState *dev)
static void loongson_ipi_unrealize(DeviceState *dev)
{
+ LoongsonIPIState *s = LOONGSON_IPI(dev);
+
+ g_free(s->ipi_mmio_mem);
+
loongson_ipi_common_unrealize(dev);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 06/28] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-08-06 12:51 ` [PULL 05/28] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 07/28] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() Philippe Mathieu-Daudé
` (22 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Move the IPICore structure and corresponding common fields
of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h".
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-7-philmd@linaro.org>
---
include/hw/intc/loongson_ipi.h | 17 ---------
include/hw/intc/loongson_ipi_common.h | 18 ++++++++++
hw/intc/loongson_ipi.c | 50 ++++++---------------------
hw/intc/loongson_ipi_common.c | 42 ++++++++++++++++++++++
4 files changed, 70 insertions(+), 57 deletions(-)
diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h
index 5a52dfbf4d..4e517cc8dc 100644
--- a/include/hw/intc/loongson_ipi.h
+++ b/include/hw/intc/loongson_ipi.h
@@ -12,22 +12,9 @@
#include "hw/intc/loongson_ipi_common.h"
#include "hw/sysbus.h"
-#define IPI_MBX_NUM 4
-
#define TYPE_LOONGSON_IPI "loongson_ipi"
OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
-typedef struct IPICore {
- LoongsonIPIState *ipi;
- uint32_t status;
- uint32_t en;
- uint32_t set;
- uint32_t clear;
- /* 64bit buf divide into 2 32bit buf */
- uint32_t buf[IPI_MBX_NUM * 2];
- qemu_irq irq;
-} IPICore;
-
struct LoongsonIPIClass {
LoongsonIPICommonClass parent_class;
@@ -39,10 +26,6 @@ struct LoongsonIPIState {
LoongsonIPICommonState parent_obj;
MemoryRegion *ipi_mmio_mem;
- MemoryRegion ipi_iocsr_mem;
- MemoryRegion ipi64_iocsr_mem;
- uint32_t num_cpu;
- IPICore *cpu;
};
#endif
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index b43b77bda6..967c70ad1c 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -11,12 +11,30 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#define IPI_MBX_NUM 4
+
#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
+typedef struct IPICore {
+ LoongsonIPICommonState *ipi;
+ uint32_t status;
+ uint32_t en;
+ uint32_t set;
+ uint32_t clear;
+ /* 64bit buf divide into 2 32-bit buf */
+ uint32_t buf[IPI_MBX_NUM * 2];
+ qemu_irq irq;
+} IPICore;
+
struct LoongsonIPICommonState {
SysBusDevice parent_obj;
+
+ MemoryRegion ipi_iocsr_mem;
+ MemoryRegion ipi64_iocsr_mem;
+ uint32_t num_cpu;
+ IPICore *cpu;
};
struct LoongsonIPICommonClass {
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 03878b896f..347bc26729 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
- LoongsonIPIState *ipi = opaque;
+ LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
MemTxAttrs attrs)
{
IPICore *s = opaque;
- LoongsonIPIState *ipi = s->ipi;
+ LoongsonIPICommonState *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
- LoongsonIPIState *ipi = opaque;
+ LoongsonIPICommonState *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
@@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = {
static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
{
- LoongsonIPIState *s = LOONGSON_IPI(dev);
+ LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
+ LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev);
LoongsonIPIState *s = LOONGSON_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *local_err = NULL;
@@ -320,18 +321,19 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
return;
}
- s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu);
- for (unsigned i = 0; i < s->num_cpu; i++) {
+ s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu);
+ for (unsigned i = 0; i < sc->num_cpu; i++) {
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
+
memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev),
- &loongson_ipi_core_ops, &s->cpu[i], name, 0x48);
+ &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48);
sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]);
}
}
static void loongson_ipi_common_unrealize(DeviceState *dev)
{
- LoongsonIPIState *s = LOONGSON_IPI(dev);
+ LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
g_free(s->cpu);
}
@@ -345,36 +347,6 @@ static void loongson_ipi_unrealize(DeviceState *dev)
loongson_ipi_common_unrealize(dev);
}
-static const VMStateDescription vmstate_ipi_core = {
- .name = "ipi-single",
- .version_id = 2,
- .minimum_version_id = 2,
- .fields = (const VMStateField[]) {
- VMSTATE_UINT32(status, IPICore),
- VMSTATE_UINT32(en, IPICore),
- VMSTATE_UINT32(set, IPICore),
- VMSTATE_UINT32(clear, IPICore),
- VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static const VMStateDescription vmstate_loongson_ipi = {
- .name = TYPE_LOONGSON_IPI,
- .version_id = 2,
- .minimum_version_id = 2,
- .fields = (const VMStateField[]) {
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu,
- vmstate_ipi_core, IPICore),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static Property ipi_properties[] = {
- DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -384,8 +356,6 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
&lic->parent_realize);
device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
&lic->parent_unrealize);
- device_class_set_props(dc, ipi_properties);
- dc->vmsd = &vmstate_loongson_ipi;
}
static const TypeInfo loongson_ipi_types[] = {
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
index 43002fe556..47796f7ece 100644
--- a/hw/intc/loongson_ipi_common.c
+++ b/hw/intc/loongson_ipi_common.c
@@ -8,6 +8,47 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/intc/loongson_ipi_common.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+
+static const VMStateDescription vmstate_ipi_core = {
+ .name = "ipi-single",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT32(status, IPICore),
+ VMSTATE_UINT32(en, IPICore),
+ VMSTATE_UINT32(set, IPICore),
+ VMSTATE_UINT32(clear, IPICore),
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_loongson_ipi_common = {
+ .name = "loongson_ipi",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .fields = (const VMStateField[]) {
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState,
+ num_cpu, vmstate_ipi_core,
+ IPICore),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property ipi_common_properties[] = {
+ DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ device_class_set_props(dc, ipi_common_properties);
+ dc->vmsd = &vmstate_loongson_ipi_common;
+}
static const TypeInfo loongarch_ipi_common_types[] = {
{
@@ -15,6 +56,7 @@ static const TypeInfo loongarch_ipi_common_types[] = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LoongsonIPICommonState),
.class_size = sizeof(LoongsonIPICommonClass),
+ .class_init = loongson_ipi_common_class_init,
.abstract = true,
}
};
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 07/28] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data()
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2024-08-06 12:51 ` [PULL 06/28] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 08/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler Philippe Mathieu-Daudé
` (21 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
In order to get LoongsonIPICommonClass in send_ipi_data()
in the next commit, propagate LoongsonIPICommonState.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-8-philmd@linaro.org>
---
hw/intc/loongson_ipi.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 347bc26729..8bf16f26d4 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
return NULL;
}
-static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
- MemTxAttrs attrs)
+static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
+ uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
@@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
return MEMTX_OK;
}
-static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult mail_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
attrs.requester_id = cs->cpu_index;
- return send_ipi_data(cs, val, addr, attrs);
+ return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
+static MemTxResult any_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
@@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
/* override requester_id */
addr = val & 0xffff;
attrs.requester_id = cs->cpu_index;
- return send_ipi_data(cs, val, addr, attrs);
+ return send_ipi_data(ipi, cs, val, addr, attrs);
}
static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
@@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = {
static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
+ LoongsonIPICommonState *ipi = opaque;
MemTxResult ret = MEMTX_OK;
addr &= 0xfff;
switch (addr) {
case MAIL_SEND_OFFSET:
- ret = mail_send(val, attrs);
+ ret = mail_send(ipi, val, attrs);
break;
case ANY_SEND_OFFSET:
- ret = any_send(val, attrs);
+ ret = any_send(ipi, val, attrs);
break;
default:
break;
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 08/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2024-08-06 12:51 ` [PULL 07/28] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 09/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler Philippe Mathieu-Daudé
` (20 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Allow Loongson IPI implementations to have their own get_iocsr_as()
handler.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-9-philmd@linaro.org>
---
include/hw/intc/loongson_ipi_common.h | 2 ++
hw/intc/loongson_ipi.c | 16 ++++++++++++----
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index 967c70ad1c..1a2ee41cc9 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -39,6 +39,8 @@ struct LoongsonIPICommonState {
struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
+
+ AddressSpace *(*get_iocsr_as)(CPUState *cpu);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 8bf16f26d4..eb99de9068 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
return loongson_ipi_core_readl(s, addr, data, size, attrs);
}
-static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
-{
#ifdef TARGET_LOONGARCH64
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
#endif
+
#ifdef TARGET_MIPS
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
return &MIPS_CPU(cpu)->env.iocsr.as;
}
-#endif
+
return NULL;
}
+#endif
static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
uint64_t val, hwaddr addr, MemTxAttrs attrs)
{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int i, mask = 0, data = 0;
- AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
+ AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
if (!iocsr_as) {
return MEMTX_DECODE_ERROR;
@@ -354,11 +360,13 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
device_class_set_parent_realize(dc, loongson_ipi_realize,
&lic->parent_realize);
device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
&lic->parent_unrealize);
+ licc->get_iocsr_as = get_iocsr_as;
}
static const TypeInfo loongson_ipi_types[] = {
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 09/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2024-08-06 12:51 ` [PULL 08/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 10/28] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers Philippe Mathieu-Daudé
` (19 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Allow Loongson IPI implementations to have their own
cpu_by_arch_id() handler.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-10-philmd@linaro.org>
---
include/hw/intc/loongson_ipi_common.h | 1 +
hw/intc/loongson_ipi.c | 10 +++++++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index 1a2ee41cc9..8997676f0d 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -41,6 +41,7 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
+ CPUState *(*cpu_by_arch_id)(int64_t id);
};
/* Mainy used by iocsr read and write */
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index eb99de9068..4a8e743528 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
static MemTxResult mail_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
- cs = cpu_by_arch_id(cpuid);
+ cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
static MemTxResult any_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs)
{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
- cs = cpu_by_arch_id(cpuid);
+ cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int index = 0;
uint32_t cpuid;
uint8_t vector;
@@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
- cs = cpu_by_arch_id(cpuid);
+ cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
@@ -367,6 +370,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
&lic->parent_unrealize);
licc->get_iocsr_as = get_iocsr_as;
+ licc->cpu_by_arch_id = cpu_by_arch_id;
}
static const TypeInfo loongson_ipi_types[] = {
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 10/28] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2024-08-06 12:51 ` [PULL 09/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 11/28] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c Philippe Mathieu-Daudé
` (18 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
In order to access loongson_ipi_core_read/write helpers
from loongson_ipi_common.c in the next commit, make their
prototype declaration public.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-11-philmd@linaro.org>
---
include/hw/intc/loongson_ipi_common.h | 6 ++++++
hw/intc/loongson_ipi.c | 10 ++++------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index 8997676f0d..65f8ef7957 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -10,6 +10,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
+#include "exec/memattrs.h"
#define IPI_MBX_NUM 4
@@ -44,6 +45,11 @@ struct LoongsonIPICommonClass {
CPUState *(*cpu_by_arch_id)(int64_t id);
};
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs);
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs);
+
/* Mainy used by iocsr read and write */
#define SMP_IPI_MAILBOX 0x1000ULL
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 4a8e743528..c13cb5a1d2 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,9 +24,8 @@
#endif
#include "trace.h"
-static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
uint64_t ret = 0;
@@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi,
return send_ipi_data(ipi, cs, val, addr, attrs);
}
-static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
- uint64_t val, unsigned size,
- MemTxAttrs attrs)
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
{
IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi;
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 11/28] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2024-08-06 12:51 ` [PULL 10/28] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 12/28] hw/intc/loongarch_ipi: Add loongarch IPI support Philippe Mathieu-Daudé
` (17 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Move the common code from loongson_ipi.c to loongson_ipi_common.c,
call parent_realize() instead of loongson_ipi_common_realize() in
loongson_ipi_realize().
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-12-philmd@linaro.org>
---
include/hw/intc/loongson_ipi_common.h | 2 +
hw/intc/loongson_ipi.c | 279 +------------------------
hw/intc/loongson_ipi_common.c | 283 ++++++++++++++++++++++++++
3 files changed, 289 insertions(+), 275 deletions(-)
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index 65f8ef7957..df9d9c5168 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -41,6 +41,8 @@ struct LoongsonIPICommonState {
struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class;
+ DeviceRealize parent_realize;
+ DeviceUnrealize parent_unrealize;
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
CPUState *(*cpu_by_arch_id)(int64_t id);
};
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index c13cb5a1d2..0b88ae3230 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -24,56 +24,6 @@
#endif
#include "trace.h"
-MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
- unsigned size, MemTxAttrs attrs)
-{
- IPICore *s = opaque;
- uint64_t ret = 0;
- int index = 0;
-
- addr &= 0xff;
- switch (addr) {
- case CORE_STATUS_OFF:
- ret = s->status;
- break;
- case CORE_EN_OFF:
- ret = s->en;
- break;
- case CORE_SET_OFF:
- ret = 0;
- break;
- case CORE_CLEAR_OFF:
- ret = 0;
- break;
- case CORE_BUF_20 ... CORE_BUF_38 + 4:
- index = (addr - CORE_BUF_20) >> 2;
- ret = s->buf[index];
- break;
- default:
- qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
- break;
- }
-
- trace_loongson_ipi_read(size, (uint64_t)addr, ret);
- *data = ret;
- return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
- uint64_t *data,
- unsigned size, MemTxAttrs attrs)
-{
- LoongsonIPICommonState *ipi = opaque;
- IPICore *s;
-
- if (attrs.requester_id >= ipi->num_cpu) {
- return MEMTX_DECODE_ERROR;
- }
-
- s = &ipi->cpu[attrs.requester_id];
- return loongson_ipi_core_readl(s, addr, data, size, attrs);
-}
-
#ifdef TARGET_LOONGARCH64
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
@@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
}
#endif
-static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
- uint64_t val, hwaddr addr, MemTxAttrs attrs)
-{
- LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
- int i, mask = 0, data = 0;
- AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
-
- if (!iocsr_as) {
- return MEMTX_DECODE_ERROR;
- }
-
- /*
- * bit 27-30 is mask for byte writing,
- * if the mask is 0, we need not to do anything.
- */
- if ((val >> 27) & 0xf) {
- data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
- for (i = 0; i < 4; i++) {
- /* get mask for byte writing */
- if (val & (0x1 << (27 + i))) {
- mask |= 0xff << (i * 8);
- }
- }
- }
-
- data &= mask;
- data |= (val >> 32) & ~mask;
- address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
-
- return MEMTX_OK;
-}
-
-static MemTxResult mail_send(LoongsonIPICommonState *ipi,
- uint64_t val, MemTxAttrs attrs)
-{
- LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
- uint32_t cpuid;
- hwaddr addr;
- CPUState *cs;
-
- cpuid = extract32(val, 16, 10);
- cs = licc->cpu_by_arch_id(cpuid);
- if (cs == NULL) {
- return MEMTX_DECODE_ERROR;
- }
-
- /* override requester_id */
- addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
- attrs.requester_id = cs->cpu_index;
- return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-static MemTxResult any_send(LoongsonIPICommonState *ipi,
- uint64_t val, MemTxAttrs attrs)
-{
- LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
- uint32_t cpuid;
- hwaddr addr;
- CPUState *cs;
-
- cpuid = extract32(val, 16, 10);
- cs = licc->cpu_by_arch_id(cpuid);
- if (cs == NULL) {
- return MEMTX_DECODE_ERROR;
- }
-
- /* override requester_id */
- addr = val & 0xffff;
- attrs.requester_id = cs->cpu_index;
- return send_ipi_data(ipi, cs, val, addr, attrs);
-}
-
-MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
- unsigned size, MemTxAttrs attrs)
-{
- IPICore *s = opaque;
- LoongsonIPICommonState *ipi = s->ipi;
- LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
- int index = 0;
- uint32_t cpuid;
- uint8_t vector;
- CPUState *cs;
-
- addr &= 0xff;
- trace_loongson_ipi_write(size, (uint64_t)addr, val);
- switch (addr) {
- case CORE_STATUS_OFF:
- qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
- break;
- case CORE_EN_OFF:
- s->en = val;
- break;
- case CORE_SET_OFF:
- s->status |= val;
- if (s->status != 0 && (s->status & s->en) != 0) {
- qemu_irq_raise(s->irq);
- }
- break;
- case CORE_CLEAR_OFF:
- s->status &= ~val;
- if (s->status == 0 && s->en != 0) {
- qemu_irq_lower(s->irq);
- }
- break;
- case CORE_BUF_20 ... CORE_BUF_38 + 4:
- index = (addr - CORE_BUF_20) >> 2;
- s->buf[index] = val;
- break;
- case IOCSR_IPI_SEND:
- cpuid = extract32(val, 16, 10);
- /* IPI status vector */
- vector = extract8(val, 0, 5);
- cs = licc->cpu_by_arch_id(cpuid);
- if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
- return MEMTX_DECODE_ERROR;
- }
- loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
- BIT(vector), 4, attrs);
- break;
- default:
- qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
- break;
- }
-
- return MEMTX_OK;
-}
-
-static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
- uint64_t val, unsigned size,
- MemTxAttrs attrs)
-{
- LoongsonIPICommonState *ipi = opaque;
- IPICore *s;
-
- if (attrs.requester_id >= ipi->num_cpu) {
- return MEMTX_DECODE_ERROR;
- }
-
- s = &ipi->cpu[attrs.requester_id];
- return loongson_ipi_core_writel(s, addr, val, size, attrs);
-}
-
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
.write_with_attrs = loongson_ipi_core_writel,
@@ -244,88 +52,15 @@ static const MemoryRegionOps loongson_ipi_core_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static const MemoryRegionOps loongson_ipi_iocsr_ops = {
- .read_with_attrs = loongson_ipi_iocsr_readl,
- .write_with_attrs = loongson_ipi_iocsr_writel,
- .impl.min_access_size = 4,
- .impl.max_access_size = 4,
- .valid.min_access_size = 4,
- .valid.max_access_size = 8,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-/* mail send and any send only support writeq */
-static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
- unsigned size, MemTxAttrs attrs)
-{
- LoongsonIPICommonState *ipi = opaque;
- MemTxResult ret = MEMTX_OK;
-
- addr &= 0xfff;
- switch (addr) {
- case MAIL_SEND_OFFSET:
- ret = mail_send(ipi, val, attrs);
- break;
- case ANY_SEND_OFFSET:
- ret = any_send(ipi, val, attrs);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-static const MemoryRegionOps loongson_ipi64_ops = {
- .write_with_attrs = loongson_ipi_writeq,
- .impl.min_access_size = 8,
- .impl.max_access_size = 8,
- .valid.min_access_size = 8,
- .valid.max_access_size = 8,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
-{
- LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- int i;
-
- if (s->num_cpu == 0) {
- error_setg(errp, "num-cpu must be at least 1");
- return;
- }
-
- memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
- &loongson_ipi_iocsr_ops,
- s, "loongson_ipi_iocsr", 0x48);
-
- /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */
- s->ipi_iocsr_mem.disable_reentrancy_guard = true;
-
- sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
-
- memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev),
- &loongson_ipi64_ops,
- s, "loongson_ipi64_iocsr", 0x118);
- sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
-
- s->cpu = g_new0(IPICore, s->num_cpu);
- for (i = 0; i < s->num_cpu; i++) {
- s->cpu[i].ipi = s;
-
- qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
- }
-}
-
static void loongson_ipi_realize(DeviceState *dev, Error **errp)
{
LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev);
LoongsonIPIState *s = LOONGSON_IPI(dev);
+ LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *local_err = NULL;
- loongson_ipi_common_realize(dev, &local_err);
+ lic->parent_realize(dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -341,20 +76,14 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
}
}
-static void loongson_ipi_common_unrealize(DeviceState *dev)
-{
- LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
-
- g_free(s->cpu);
-}
-
static void loongson_ipi_unrealize(DeviceState *dev)
{
LoongsonIPIState *s = LOONGSON_IPI(dev);
+ LoongsonIPIClass *k = LOONGSON_IPI_GET_CLASS(dev);
g_free(s->ipi_mmio_mem);
- loongson_ipi_common_unrealize(dev);
+ k->parent_unrealize(dev);
}
static void loongson_ipi_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c
index 47796f7ece..a6ce0181f6 100644
--- a/hw/intc/loongson_ipi_common.c
+++ b/hw/intc/loongson_ipi_common.c
@@ -8,8 +8,286 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/intc/loongson_ipi_common.h"
+#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
#include "migration/vmstate.h"
+#include "trace.h"
+
+MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ IPICore *s = opaque;
+ uint64_t ret = 0;
+ int index = 0;
+
+ addr &= 0xff;
+ switch (addr) {
+ case CORE_STATUS_OFF:
+ ret = s->status;
+ break;
+ case CORE_EN_OFF:
+ ret = s->en;
+ break;
+ case CORE_SET_OFF:
+ ret = 0;
+ break;
+ case CORE_CLEAR_OFF:
+ ret = 0;
+ break;
+ case CORE_BUF_20 ... CORE_BUF_38 + 4:
+ index = (addr - CORE_BUF_20) >> 2;
+ ret = s->buf[index];
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
+ break;
+ }
+
+ trace_loongson_ipi_read(size, (uint64_t)addr, ret);
+ *data = ret;
+
+ return MEMTX_OK;
+}
+
+static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ LoongsonIPICommonState *ipi = opaque;
+ IPICore *s;
+
+ if (attrs.requester_id >= ipi->num_cpu) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ s = &ipi->cpu[attrs.requester_id];
+ return loongson_ipi_core_readl(s, addr, data, size, attrs);
+}
+
+static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
+ uint64_t val, hwaddr addr, MemTxAttrs attrs)
+{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
+ int i, mask = 0, data = 0;
+ AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
+
+ if (!iocsr_as) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ /*
+ * bit 27-30 is mask for byte writing,
+ * if the mask is 0, we need not to do anything.
+ */
+ if ((val >> 27) & 0xf) {
+ data = address_space_ldl_le(iocsr_as, addr, attrs, NULL);
+ for (i = 0; i < 4; i++) {
+ /* get mask for byte writing */
+ if (val & (0x1 << (27 + i))) {
+ mask |= 0xff << (i * 8);
+ }
+ }
+ }
+
+ data &= mask;
+ data |= (val >> 32) & ~mask;
+ address_space_stl_le(iocsr_as, addr, data, attrs, NULL);
+
+ return MEMTX_OK;
+}
+
+static MemTxResult mail_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
+{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
+ uint32_t cpuid;
+ hwaddr addr;
+ CPUState *cs;
+
+ cpuid = extract32(val, 16, 10);
+ cs = licc->cpu_by_arch_id(cpuid);
+ if (cs == NULL) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ /* override requester_id */
+ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
+ attrs.requester_id = cs->cpu_index;
+ return send_ipi_data(ipi, cs, val, addr, attrs);
+}
+
+static MemTxResult any_send(LoongsonIPICommonState *ipi,
+ uint64_t val, MemTxAttrs attrs)
+{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
+ uint32_t cpuid;
+ hwaddr addr;
+ CPUState *cs;
+
+ cpuid = extract32(val, 16, 10);
+ cs = licc->cpu_by_arch_id(cpuid);
+ if (cs == NULL) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ /* override requester_id */
+ addr = val & 0xffff;
+ attrs.requester_id = cs->cpu_index;
+ return send_ipi_data(ipi, cs, val, addr, attrs);
+}
+
+MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
+{
+ IPICore *s = opaque;
+ LoongsonIPICommonState *ipi = s->ipi;
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
+ int index = 0;
+ uint32_t cpuid;
+ uint8_t vector;
+ CPUState *cs;
+
+ addr &= 0xff;
+ trace_loongson_ipi_write(size, (uint64_t)addr, val);
+ switch (addr) {
+ case CORE_STATUS_OFF:
+ qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
+ break;
+ case CORE_EN_OFF:
+ s->en = val;
+ break;
+ case CORE_SET_OFF:
+ s->status |= val;
+ if (s->status != 0 && (s->status & s->en) != 0) {
+ qemu_irq_raise(s->irq);
+ }
+ break;
+ case CORE_CLEAR_OFF:
+ s->status &= ~val;
+ if (s->status == 0 && s->en != 0) {
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ case CORE_BUF_20 ... CORE_BUF_38 + 4:
+ index = (addr - CORE_BUF_20) >> 2;
+ s->buf[index] = val;
+ break;
+ case IOCSR_IPI_SEND:
+ cpuid = extract32(val, 16, 10);
+ /* IPI status vector */
+ vector = extract8(val, 0, 5);
+ cs = licc->cpu_by_arch_id(cpuid);
+ if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
+ return MEMTX_DECODE_ERROR;
+ }
+ loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
+ BIT(vector), 4, attrs);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
+ break;
+ }
+
+ return MEMTX_OK;
+}
+
+static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
+{
+ LoongsonIPICommonState *ipi = opaque;
+ IPICore *s;
+
+ if (attrs.requester_id >= ipi->num_cpu) {
+ return MEMTX_DECODE_ERROR;
+ }
+
+ s = &ipi->cpu[attrs.requester_id];
+ return loongson_ipi_core_writel(s, addr, val, size, attrs);
+}
+
+static const MemoryRegionOps loongson_ipi_iocsr_ops = {
+ .read_with_attrs = loongson_ipi_iocsr_readl,
+ .write_with_attrs = loongson_ipi_iocsr_writel,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* mail send and any send only support writeq */
+static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size, MemTxAttrs attrs)
+{
+ LoongsonIPICommonState *ipi = opaque;
+ MemTxResult ret = MEMTX_OK;
+
+ addr &= 0xfff;
+ switch (addr) {
+ case MAIL_SEND_OFFSET:
+ ret = mail_send(ipi, val, attrs);
+ break;
+ case ANY_SEND_OFFSET:
+ ret = any_send(ipi, val, attrs);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const MemoryRegionOps loongson_ipi64_ops = {
+ .write_with_attrs = loongson_ipi_writeq,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void loongson_ipi_common_realize(DeviceState *dev, Error **errp)
+{
+ LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ int i;
+
+ if (s->num_cpu == 0) {
+ error_setg(errp, "num-cpu must be at least 1");
+ return;
+ }
+
+ memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
+ &loongson_ipi_iocsr_ops,
+ s, "loongson_ipi_iocsr", 0x48);
+
+ /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */
+ s->ipi_iocsr_mem.disable_reentrancy_guard = true;
+
+ sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
+
+ memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev),
+ &loongson_ipi64_ops,
+ s, "loongson_ipi64_iocsr", 0x118);
+ sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
+
+ s->cpu = g_new0(IPICore, s->num_cpu);
+ for (i = 0; i < s->num_cpu; i++) {
+ s->cpu[i].ipi = s;
+
+ qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
+ }
+}
+
+static void loongson_ipi_common_unrealize(DeviceState *dev)
+{
+ LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev);
+
+ g_free(s->cpu);
+}
static const VMStateDescription vmstate_ipi_core = {
.name = "ipi-single",
@@ -45,7 +323,12 @@ static Property ipi_common_properties[] = {
static void loongson_ipi_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+ device_class_set_parent_realize(dc, loongson_ipi_common_realize,
+ &licc->parent_realize);
+ device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize,
+ &licc->parent_unrealize);
device_class_set_props(dc, ipi_common_properties);
dc->vmsd = &vmstate_loongson_ipi_common;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 12/28] hw/intc/loongarch_ipi: Add loongarch IPI support
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2024-08-06 12:51 ` [PULL 11/28] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 13/28] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI Philippe Mathieu-Daudé
` (16 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with KVM mode.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Rebased and simplified]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-13-philmd@linaro.org>
---
include/hw/intc/loongarch_ipi.h | 25 ++++++++++++
hw/intc/loongarch_ipi.c | 68 +++++++++++++++++++++++++++++++++
hw/intc/Kconfig | 4 ++
hw/intc/meson.build | 1 +
4 files changed, 98 insertions(+)
create mode 100644 include/hw/intc/loongarch_ipi.h
create mode 100644 hw/intc/loongarch_ipi.c
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
new file mode 100644
index 0000000000..276b3040a3
--- /dev/null
+++ b/include/hw/intc/loongarch_ipi.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch IPI interrupt header files
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_IPI_H
+#define HW_LOONGARCH_IPI_H
+
+#include "qom/object.h"
+#include "hw/intc/loongson_ipi_common.h"
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI)
+
+struct LoongarchIPIState {
+ LoongsonIPICommonState parent_obj;
+};
+
+struct LoongarchIPIClass {
+ LoongsonIPICommonClass parent_class;
+};
+
+#endif
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
new file mode 100644
index 0000000000..2ae1a42c46
--- /dev/null
+++ b/hw/intc/loongarch_ipi.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch IPI interrupt support
+ *
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/intc/loongarch_ipi.h"
+#include "target/loongarch/cpu.h"
+
+static AddressSpace *get_iocsr_as(CPUState *cpu)
+{
+ return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
+}
+
+static int archid_cmp(const void *a, const void *b)
+{
+ CPUArchId *archid_a = (CPUArchId *)a;
+ CPUArchId *archid_b = (CPUArchId *)b;
+
+ return archid_a->arch_id - archid_b->arch_id;
+}
+
+static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
+{
+ CPUArchId apic_id, *found_cpu;
+
+ apic_id.arch_id = id;
+ found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
+ ms->possible_cpus->len,
+ sizeof(*ms->possible_cpus->cpus),
+ archid_cmp);
+
+ return found_cpu;
+}
+
+static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id)
+{
+ MachineState *machine = MACHINE(qdev_get_machine());
+ CPUArchId *archid;
+
+ archid = find_cpu_by_archid(machine, arch_id);
+ if (archid) {
+ return CPU(archid->cpu);
+ }
+
+ return NULL;
+}
+
+static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
+{
+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
+
+ licc->get_iocsr_as = get_iocsr_as;
+ licc->cpu_by_arch_id = loongarch_cpu_by_arch_id;
+}
+
+static const TypeInfo loongarch_ipi_types[] = {
+ {
+ .name = TYPE_LOONGARCH_IPI,
+ .parent = TYPE_LOONGSON_IPI_COMMON,
+ .class_init = loongarch_ipi_class_init,
+ }
+};
+
+DEFINE_TYPES(loongarch_ipi_types)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index a2a0fdca85..dd405bdb5d 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -94,6 +94,10 @@ config LOONGSON_IPI
bool
select LOONGSON_IPI_COMMON
+config LOONGARCH_IPI
+ bool
+ select LOONGSON_IPI_COMMON
+
config LOONGARCH_PCH_PIC
bool
select UNIMP
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index a09a527207..f4d81eb8e4 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 13/28] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2024-08-06 12:51 ` [PULL 12/28] hw/intc/loongarch_ipi: Add loongarch IPI support Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 14/28] hw/intc/loongson_ipi: Restrict to MIPS Philippe Mathieu-Daudé
` (15 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Loongarch IPI inherits from class LoongsonIPICommonClass, and it
only contains Loongarch 3A5000 virt machine specific interfaces,
rather than mix different machine implementations together.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Rebased]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-14-philmd@linaro.org>
---
include/hw/loongarch/virt.h | 1 -
hw/loongarch/virt.c | 4 ++--
hw/loongarch/Kconfig | 2 +-
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index 603c1cebdb..c373e48f27 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -11,7 +11,6 @@
#include "target/loongarch/cpu.h"
#include "hw/boards.h"
#include "qemu/queue.h"
-#include "hw/intc/loongson_ipi.h"
#include "hw/block/flash.h"
#include "hw/loongarch/boot.h"
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e592b1b6b7..29040422aa 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -23,7 +23,7 @@
#include "net/net.h"
#include "hw/loader.h"
#include "elf.h"
-#include "hw/intc/loongson_ipi.h"
+#include "hw/intc/loongarch_ipi.h"
#include "hw/intc/loongarch_extioi.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
@@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
*/
/* Create IPI device */
- ipi = qdev_new(TYPE_LOONGSON_IPI);
+ ipi = qdev_new(TYPE_LOONGARCH_IPI);
qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 89be737726..0de713a439 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -12,7 +12,7 @@ config LOONGARCH_VIRT
select SERIAL
select VIRTIO_PCI
select PLATFORM_BUS
- select LOONGSON_IPI
+ select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
select LOONGARCH_EXTIOI
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 14/28] hw/intc/loongson_ipi: Restrict to MIPS
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2024-08-06 12:51 ` [PULL 13/28] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 15/28] hw/sd/sdcard: Explicit dummy byte value Philippe Mathieu-Daudé
` (14 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Bibo Mao, Philippe Mathieu-Daudé, Song Gao,
Richard Henderson, Jiaxun Yang
From: Bibo Mao <maobibo@loongson.cn>
Now than LoongArch target can use the TYPE_LOONGARCH_IPI
model, restrict TYPE_LOONGSON_IPI to MIPS.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-15-philmd@linaro.org>
---
MAINTAINERS | 2 --
hw/intc/loongson_ipi.c | 14 --------------
2 files changed, 16 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ca701cf0c..74a85360fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1251,10 +1251,8 @@ F: hw/loongarch/
F: include/hw/loongarch/virt.h
F: include/hw/intc/loongarch_*.h
F: include/hw/intc/loongson_ipi_common.h
-F: include/hw/intc/loongson_ipi.h
F: hw/intc/loongarch_*.c
F: hw/intc/loongson_ipi_common.c
-F: hw/intc/loongson_ipi.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
F: gdb-xml/loongarch*.xml
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 0b88ae3230..8382ceca67 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/loongson_ipi.c
@@ -16,22 +16,9 @@
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "migration/vmstate.h"
-#ifdef TARGET_LOONGARCH64
-#include "target/loongarch/cpu.h"
-#endif
-#ifdef TARGET_MIPS
#include "target/mips/cpu.h"
-#endif
#include "trace.h"
-#ifdef TARGET_LOONGARCH64
-static AddressSpace *get_iocsr_as(CPUState *cpu)
-{
- return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
-}
-#endif
-
-#ifdef TARGET_MIPS
static AddressSpace *get_iocsr_as(CPUState *cpu)
{
if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
@@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu)
return NULL;
}
-#endif
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 15/28] hw/sd/sdcard: Explicit dummy byte value
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2024-08-06 12:51 ` [PULL 14/28] hw/intc/loongson_ipi: Restrict to MIPS Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 16/28] hw/sd/sdcard: Do not abort when reading DAT lines on invalid cmd state Philippe Mathieu-Daudé
` (13 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
On error the DAT lines are left unmodified to their
previous states. QEMU returns 0x00 for convenience.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240730092138.32443-2-philmd@linaro.org>
---
hw/sd/sd.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 07cb97d88c..de27e34fc8 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -2478,20 +2478,22 @@ void sd_write_byte(SDState *sd, uint8_t value)
uint8_t sd_read_byte(SDState *sd)
{
/* TODO: Append CRCs */
+ const uint8_t dummy_byte = 0x00;
uint8_t ret;
uint32_t io_len;
if (!sd->blk || !blk_is_inserted(sd->blk) || !sd->enable)
- return 0x00;
+ return dummy_byte;
if (sd->state != sd_sendingdata_state) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: not in Sending-Data state\n", __func__);
- return 0x00;
+ return dummy_byte;
}
- if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION))
- return 0x00;
+ if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION)) {
+ return dummy_byte;
+ }
io_len = sd_blk_len(sd);
@@ -2517,7 +2519,7 @@ uint8_t sd_read_byte(SDState *sd)
if (sd->data_offset == 0) {
if (!address_in_range(sd, "READ_MULTIPLE_BLOCK",
sd->data_start, io_len)) {
- return 0x00;
+ return dummy_byte;
}
sd_blk_read(sd, sd->data_start, io_len);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 16/28] hw/sd/sdcard: Do not abort when reading DAT lines on invalid cmd state
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2024-08-06 12:51 ` [PULL 15/28] hw/sd/sdcard: Explicit dummy byte value Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-11 7:41 ` Michael Tokarev
2024-08-06 12:51 ` [PULL 17/28] hw/sd/sdhci: Reset @data_count index on invalid ADMA transfers Philippe Mathieu-Daudé
` (12 subsequent siblings)
28 siblings, 1 reply; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, qemu-stable, Zheyu Ma,
Richard Henderson
Guest should not try to read the DAT lines from invalid
command state. If it still insists to do so, return a
dummy value.
Cc: qemu-stable@nongnu.org
Fixes: e2dec2eab0 ("hw/sd/sdcard: Remove default case in read/write on DAT lines")
Reported-by: Zheyu Ma <zheyuma97@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2454
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240730092138.32443-3-philmd@linaro.org>
---
hw/sd/sd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index de27e34fc8..a140a32ccd 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -2540,7 +2540,9 @@ uint8_t sd_read_byte(SDState *sd)
break;
default:
- g_assert_not_reached();
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DAT read illegal for command %s\n",
+ __func__, sd->last_cmd_name);
+ return dummy_byte;
}
return ret;
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 17/28] hw/sd/sdhci: Reset @data_count index on invalid ADMA transfers
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2024-08-06 12:51 ` [PULL 16/28] hw/sd/sdcard: Do not abort when reading DAT lines on invalid cmd state Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 18/28] hw/block/pflash_cfi01: Don't decrement pfl->counter below 0 Philippe Mathieu-Daudé
` (11 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, qemu-stable, Zheyu Ma,
Richard Henderson
We neglected to clear the @data_count index on ADMA error,
allowing to trigger assertion in sdhci_read_dataport() or
sdhci_write_dataport().
Cc: qemu-stable@nongnu.org
Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller")
Reported-by: Zheyu Ma <zheyuma97@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2455
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240730092138.32443-4-philmd@linaro.org>
---
hw/sd/sdhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index d02c3e3963..8293d83556 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -846,6 +846,7 @@ static void sdhci_do_adma(SDHCIState *s)
}
}
if (res != MEMTX_OK) {
+ s->data_count = 0;
if (s->errintstsen & SDHC_EISEN_ADMAERR) {
trace_sdhci_error("Set ADMA error flag");
s->errintsts |= SDHC_EIS_ADMAERR;
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 18/28] hw/block/pflash_cfi01: Don't decrement pfl->counter below 0
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2024-08-06 12:51 ` [PULL 17/28] hw/sd/sdhci: Reset @data_count index on invalid ADMA transfers Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 19/28] hw/ide/atapi: Be explicit that assigning to s->lcyl truncates Philippe Mathieu-Daudé
` (10 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Kevin Wolf, Philippe Mathieu-Daudé
From: Peter Maydell <peter.maydell@linaro.org>
In pflash_write() Coverity points out that we can decrement the
unsigned pfl->counter below zero, which makes it wrap around. In
fact this is harmless, because if pfl->counter is 0 at this point we
also increment pfl->wcycle to 3, and the wcycle == 3 handling doesn't
look at counter; the only way back into code which looks at the
counter value is via wcycle == 1, which will reinitialize the counter.
But it's arguably a little clearer to break early in the "counter ==
0" if(), to avoid the decrement-below-zero.
Resolves: Coverity CID 1547611
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20240731143617.3391947-4-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/block/pflash_cfi01.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index c8f1cf5a87..2f3d1dd509 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -614,6 +614,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
if (!pfl->counter) {
trace_pflash_write(pfl->name, "block write finished");
pfl->wcycle++;
+ break;
}
pfl->counter--;
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 19/28] hw/ide/atapi: Be explicit that assigning to s->lcyl truncates
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2024-08-06 12:51 ` [PULL 18/28] hw/block/pflash_cfi01: Don't decrement pfl->counter below 0 Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 20/28] hw/block/fdc-isa: Assert that isa_fdc_get_drive_max_chs() found something Philippe Mathieu-Daudé
` (9 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Markus Armbruster, Kevin Wolf,
Philippe Mathieu-Daudé
From: Peter Maydell <peter.maydell@linaro.org>
In ide_atapi_cmd_reply_end() we calculate a 16-bit size, and then
assign its two halves to s->lcyl and s->hcyl like this:
s->lcyl = size;
s->hcyl = size >> 8;
Coverity warns that the first line here can overflow the
8-bit s->lcyl variable. This is true, and in this case we're
deliberately only after the low 8 bits of the value. The
code is clearer to both humans and Coverity if we're explicit
that we only wanted the low 8 bits, though.
Resolves: Coverity CID 1547621
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20240731143617.3391947-5-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/ide/atapi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index fcb6cca157..e82959dc2d 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -265,7 +265,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
byte_count_limit--;
size = byte_count_limit;
}
- s->lcyl = size;
+ s->lcyl = size & 0xff;
s->hcyl = size >> 8;
s->elementary_transfer_size = size;
/* we cannot transmit more than one sector at a time */
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 20/28] hw/block/fdc-isa: Assert that isa_fdc_get_drive_max_chs() found something
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2024-08-06 12:51 ` [PULL 19/28] hw/ide/atapi: Be explicit that assigning to s->lcyl truncates Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 21/28] hw/ide/pci: Remove dead code from bmdma_prepare_buf() Philippe Mathieu-Daudé
` (8 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Markus Armbruster, Kevin Wolf,
Philippe Mathieu-Daudé
From: Peter Maydell <peter.maydell@linaro.org>
Coverity complains about an overflow in isa_fdc_get_drive_max_chs()
that can happen if the loop over fd_formats never finds a match,
because we initialize *maxc to 0 and then at the end of the
function decrement it.
This can't ever actually happen because fd_formats has at least
one entry for each FloppyDriveType, so we must at least once
find a match and update *maxc, *maxh and *maxs. Assert that we
did find a match, which should keep Coverity happy and will also
detect possible bugs in the data in fd_formats.
Resolves: Coverity CID 1547663
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240731143617.3391947-6-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/block/fdc-isa.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c
index e43dc532af..796835f57b 100644
--- a/hw/block/fdc-isa.c
+++ b/hw/block/fdc-isa.c
@@ -147,6 +147,8 @@ static void isa_fdc_get_drive_max_chs(FloppyDriveType type, uint8_t *maxc,
*maxs = fdf->last_sect;
}
}
+ /* fd_formats must contain at least one entry per FloppyDriveType */
+ assert(*maxc);
(*maxc)--;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 21/28] hw/ide/pci: Remove dead code from bmdma_prepare_buf()
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2024-08-06 12:51 ` [PULL 20/28] hw/block/fdc-isa: Assert that isa_fdc_get_drive_max_chs() found something Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 22/28] hw/display/virtio-gpu: Improve "opengl is not available" error message Philippe Mathieu-Daudé
` (7 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Kevin Wolf, Philippe Mathieu-Daudé,
Richard Henderson
From: Peter Maydell <peter.maydell@linaro.org>
Coverity notes that the code at the end of the loop in
bmdma_prepare_buf() is unreachable. This is because in commit
9fbf0fa81fca8f527 ("ide: remove hardcoded 2GiB transactional limit")
we removed the only codepath in the loop which could "break" out of
it, but didn't notice that this meant we should also remove the code
at the end of the loop.
Remove the dead code.
Resolves: Coverity CID 1547772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMD: Break and return once at EOF]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240805182419.22239-1-philmd@linaro.org>
---
hw/ide/pci.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 4675d079a1..a008fe7316 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -237,7 +237,7 @@ static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
/* end of table (with a fail safe of one page) */
if (bm->cur_prd_last ||
(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
- return s->sg.size;
+ break;
}
pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
bm->cur_addr += 8;
@@ -266,10 +266,7 @@ static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
s->io_buffer_size += l;
}
}
-
- qemu_sglist_destroy(&s->sg);
- s->io_buffer_size = 0;
- return -1;
+ return s->sg.size;
}
/* return 0 if buffer completed */
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 22/28] hw/display/virtio-gpu: Improve "opengl is not available" error message
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2024-08-06 12:51 ` [PULL 21/28] hw/ide/pci: Remove dead code from bmdma_prepare_buf() Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 23/28] system/vl.c: Expand OpenGL related errors Philippe Mathieu-Daudé
` (6 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé,
Marc-André Lureau
From: Peter Maydell <peter.maydell@linaro.org>
If the user tries to use the virtio-gpu-gl device but the display
backend doesn't have OpenGL support enabled, we currently print a
rather uninformative error message:
$ qemu-system-aarch64 -M virt -device virtio-gpu-gl
qemu-system-aarch64: -device virtio-gpu-gl: opengl is not available
Since OpenGL is not enabled on display frontends by default, users
are quite likely to run into this. Improve the error message to
be more specific and to suggest to the user a path forward.
Note that the case of "user tried to enable OpenGL but the display
backend doesn't handle it" is caught elsewhere first, so we can
assume that isn't the problem:
$ qemu-system-aarch64 -M virt -device virtio-gpu-gl -display curses,gl=on
qemu-system-aarch64: OpenGL is not supported by the display
(Use of error_append_hint() requires us to add an ERRP_GUARD() to
the function, as noted in include/qapi/error.h.)
With this commit we now produce the hopefully more helpful error:
$ ./build/x86/qemu-system-aarch64 -M virt -device virtio-gpu-gl
qemu-system-aarch64: -device virtio-gpu-gl: The display backend does not have OpenGL support enabled
It can be enabled with '-display BACKEND,gl=on' where BACKEND is the name of the display backend to use.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2443
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20240731154136.3494621-2-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/display/virtio-gpu-gl.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/virtio-gpu-gl.c
index 952820a425..29d20b0132 100644
--- a/hw/display/virtio-gpu-gl.c
+++ b/hw/display/virtio-gpu-gl.c
@@ -106,6 +106,7 @@ static void virtio_gpu_gl_reset(VirtIODevice *vdev)
static void virtio_gpu_gl_device_realize(DeviceState *qdev, Error **errp)
{
+ ERRP_GUARD();
VirtIOGPU *g = VIRTIO_GPU(qdev);
#if HOST_BIG_ENDIAN
@@ -119,7 +120,12 @@ static void virtio_gpu_gl_device_realize(DeviceState *qdev, Error **errp)
}
if (!display_opengl) {
- error_setg(errp, "opengl is not available");
+ error_setg(errp,
+ "The display backend does not have OpenGL support enabled");
+ error_append_hint(errp,
+ "It can be enabled with '-display BACKEND,gl=on' "
+ "where BACKEND is the name of the display backend "
+ "to use.\n");
return;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 23/28] system/vl.c: Expand OpenGL related errors
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2024-08-06 12:51 ` [PULL 22/28] hw/display/virtio-gpu: Improve "opengl is not available" error message Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 24/28] ui/console: Note in '-display help' that some backends support suboptions Philippe Mathieu-Daudé
` (5 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé,
Marc-André Lureau
From: Peter Maydell <peter.maydell@linaro.org>
Expand the OpenGL related error messages we produce for various
"OpenGL not present/not supported" cases, to hopefully guide the
user towards how to fix things.
Now if the user tries to enable GL on a backend that doesn't
support it the error message is a bit more precise:
$ qemu-system-aarch64 -M virt -device virtio-gpu-gl -display curses,gl=on
qemu-system-aarch64: OpenGL is not supported by display backend 'curses'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20240731154136.3494621-3-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
system/vl.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/system/vl.c b/system/vl.c
index 9e8f16f155..213ee6a6a9 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -1973,9 +1973,10 @@ static void qemu_create_early_backends(void)
if (dpy.has_gl && dpy.gl != DISPLAYGL_MODE_OFF && display_opengl == 0) {
#if defined(CONFIG_OPENGL)
- error_report("OpenGL is not supported by the display");
+ error_report("OpenGL is not supported by display backend '%s'",
+ DisplayType_str(dpy.type));
#else
- error_report("OpenGL support is disabled");
+ error_report("OpenGL support was disabled when QEMU was compiled");
#endif
exit(1);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 24/28] ui/console: Note in '-display help' that some backends support suboptions
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2024-08-06 12:51 ` [PULL 23/28] system/vl.c: Expand OpenGL related errors Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 25/28] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé
` (4 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé,
Marc-André Lureau
From: Peter Maydell <peter.maydell@linaro.org>
Currently '-display help' only prints the available backends. Some
of those backends support suboptions (e.g. '-display gtk,gl=on').
Mention that in the help output, and point the user to where they
might be able to find more information about the suboptions.
The new output looks like this:
$ qemu-system-aarch64 -display help
Available display backend types:
none
gtk
sdl
egl-headless
curses
spice-app
dbus
Some display backends support suboptions, which can be set with
-display backend,option=value,option=value...
For a short list of the suboptions for each display, see the top-level -help output; more detail is in the documentation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20240731154136.3494621-4-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
ui/console.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/ui/console.c b/ui/console.c
index e8f0083af7..105a0e2c70 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1632,4 +1632,9 @@ void qemu_display_help(void)
printf("%s\n", DisplayType_str(dpys[idx]->type));
}
}
+ printf("\n"
+ "Some display backends support suboptions, which can be set with\n"
+ " -display backend,option=value,option=value...\n"
+ "For a short list of the suboptions for each display, see the "
+ "top-level -help output; more detail is in the documentation.\n");
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 25/28] hw/pci-host/gt64120: Set PCI base address register write mask
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (23 preceding siblings ...)
2024-08-06 12:51 ` [PULL 24/28] ui/console: Note in '-display help' that some backends support suboptions Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 26/28] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé
` (3 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, BALATON Zoltan
When booting Linux we see:
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size)
This is due to missing base address register write mask.
Add it to get:
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref]
pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref]
pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff]
pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff]
pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff]
pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000fff]
Since this device is only used by MIPS machines which aren't
versioned, we don't need to update migration compat machinery.
Mention the datasheet referenced. Remove the "Malta assumptions
ahead" comment since the reset values from the datasheet are used.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20240802213122.86852-2-philmd@linaro.org>
---
hw/pci-host/gt64120.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
index e02efc9e2e..573d2619ee 100644
--- a/hw/pci-host/gt64120.c
+++ b/hw/pci-host/gt64120.c
@@ -1,6 +1,8 @@
/*
* QEMU GT64120 PCI host
*
+ * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999)
+ *
* Copyright (c) 2006,2007 Aurelien Jarno
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -1213,17 +1215,27 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
static void gt64120_pci_realize(PCIDevice *d, Error **errp)
{
- /* FIXME: Malta specific hw assumptions ahead */
+ /* Values from chapter 17.16 "PCI Configuration" */
+
pci_set_word(d->config + PCI_COMMAND, 0);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
pci_config_set_prog_interface(d->config, 0);
+
+ pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */
+ pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */
+ pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */
+ pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */
+ pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */
+ pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */
+
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
+
pci_set_byte(d->config + 0x3d, 0x01);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 26/28] hw/pci-host/gt64120: Reset config registers during RESET phase
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (24 preceding siblings ...)
2024-08-06 12:51 ` [PULL 25/28] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 27/28] docs/specs/pci-ids: Add missing devices Philippe Mathieu-Daudé
` (2 subsequent siblings)
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Michael S . Tsirkin, BALATON Zoltan
Reset config values in the device RESET phase, not only once
when the device is realized, because otherwise the device can
use unknown values at reset.
Since we are adding a new reset method, use the preferred
Resettable API (for a simple leaf device reset, a
DeviceClass::reset method and a ResettableClass::reset_hold
method are essentially identical).
Reported-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240802213122.86852-3-philmd@linaro.org>
---
hw/pci-host/gt64120.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
index 573d2619ee..33607dfbec 100644
--- a/hw/pci-host/gt64120.c
+++ b/hw/pci-host/gt64120.c
@@ -1217,17 +1217,24 @@ static void gt64120_pci_realize(PCIDevice *d, Error **errp)
{
/* Values from chapter 17.16 "PCI Configuration" */
- pci_set_word(d->config + PCI_COMMAND, 0);
- pci_set_word(d->config + PCI_STATUS,
- PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
- pci_config_set_prog_interface(d->config, 0);
-
pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */
pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */
pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */
pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */
pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */
pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */
+}
+
+static void gt64120_pci_reset_hold(Object *obj, ResetType type)
+{
+ PCIDevice *d = PCI_DEVICE(obj);
+
+ /* Values from chapter 17.16 "PCI Configuration" */
+
+ pci_set_word(d->config + PCI_COMMAND, 0);
+ pci_set_word(d->config + PCI_STATUS,
+ PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
+ pci_config_set_prog_interface(d->config, 0);
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
@@ -1243,7 +1250,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ rc->phases.hold = gt64120_pci_reset_hold;
k->realize = gt64120_pci_realize;
k->vendor_id = PCI_VENDOR_ID_MARVELL;
k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 27/28] docs/specs/pci-ids: Add missing devices
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (25 preceding siblings ...)
2024-08-06 12:51 ` [PULL 26/28] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 12:51 ` [PULL 28/28] docs/specs/pci-ids: Fix markup Philippe Mathieu-Daudé
2024-08-06 21:08 ` [PULL 00/28] Misc HW & UI patches for 2024-08-06 Richard Henderson
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: George Matsumura, Philippe Mathieu-Daudé
From: George Matsumura <gorg@gorgnet.net>
Add the missing devices 1b36:000c (PCIe root port) and 1b36:000e
(PCIe-to-PCI bridge).
Signed-off-by: George Matsumura <gorg@gorgnet.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240805031012.16547-2-gorg@gorgnet.net>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
docs/specs/pci-ids.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst
index c0a3dec2e7..0de13de1e4 100644
--- a/docs/specs/pci-ids.rst
+++ b/docs/specs/pci-ids.rst
@@ -82,8 +82,12 @@ PCI devices (other than virtio):
PCI-PCI bridge (multiseat)
1b36:000b
PCIe Expander Bridge (-device pxb-pcie)
+1b36:000c
+ PCIe Root Port (``-device pcie-root-port``)
1b36:000d
PCI xhci usb host adapter
+1b36:000e
+ PCIe-to-PCI bridge (``-device pcie-pci-bridge``)
1b36:000f
mdpy (mdev sample device), ``linux/samples/vfio-mdev/mdpy.c``
1b36:0010
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 28/28] docs/specs/pci-ids: Fix markup
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (26 preceding siblings ...)
2024-08-06 12:51 ` [PULL 27/28] docs/specs/pci-ids: Add missing devices Philippe Mathieu-Daudé
@ 2024-08-06 12:51 ` Philippe Mathieu-Daudé
2024-08-06 21:08 ` [PULL 00/28] Misc HW & UI patches for 2024-08-06 Richard Henderson
28 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-08-06 12:51 UTC (permalink / raw)
To: qemu-devel; +Cc: George Matsumura, Philippe Mathieu-Daudé
From: George Matsumura <gorg@gorgnet.net>
This fixes the markup of the PCI and PCIe Expander Bridge entries to be
consistent with the rest of the file.
Signed-off-by: George Matsumura <gorg@gorgnet.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240805031012.16547-4-gorg@gorgnet.net>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
docs/specs/pci-ids.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst
index 0de13de1e4..328ab31fe8 100644
--- a/docs/specs/pci-ids.rst
+++ b/docs/specs/pci-ids.rst
@@ -77,11 +77,11 @@ PCI devices (other than virtio):
1b36:0008
PCIe host bridge
1b36:0009
- PCI Expander Bridge (-device pxb)
+ PCI Expander Bridge (``-device pxb``)
1b36:000a
PCI-PCI bridge (multiseat)
1b36:000b
- PCIe Expander Bridge (-device pxb-pcie)
+ PCIe Expander Bridge (``-device pxb-pcie``)
1b36:000c
PCIe Root Port (``-device pcie-root-port``)
1b36:000d
--
2.45.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PULL 00/28] Misc HW & UI patches for 2024-08-06
2024-08-06 12:51 [PULL 00/28] Misc HW & UI patches for 2024-08-06 Philippe Mathieu-Daudé
` (27 preceding siblings ...)
2024-08-06 12:51 ` [PULL 28/28] docs/specs/pci-ids: Fix markup Philippe Mathieu-Daudé
@ 2024-08-06 21:08 ` Richard Henderson
28 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2024-08-06 21:08 UTC (permalink / raw)
To: qemu-devel
On 8/6/24 22:51, Philippe Mathieu-Daudé wrote:
> Hi,
>
> Bigger PR than I expected for RC2, but unfortunately
> the LoongArch Virt is broken so requires these patches
> (it took me long to figure all the issues with them).
>
> The following changes since commit e7207a9971dd41618b407030902b0b2256deb664:
>
> Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging (2024-08-06 08:02:34 +1000)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/hw-misc-20240806
>
> for you to fetch changes up to e006f0186bff4c66d3dd7a34e08fdae81d606480:
>
> docs/specs/pci-ids: Fix markup (2024-08-06 10:22:52 +0200)
>
> ----------------------------------------------------------------
> Misc HW & UI patches
>
> - Replace Loongson IPI with LoongArch IPI on LoongArch Virt machine (Bibo)
> - SD card: Do not abort when reading DAT lines on invalid cmd state (Phil)
> - SDHCI: Reset @data_count index on invalid ADMA transfers (Phil)
> - Don't decrement PFlash counter below 0 (Peter)
> - Explicit a 8bit truncate on IDE ATAPI (Peter)
> - Silent Coverity warning in ISA FDC (Peter)
> - Remove dead code in PCI IDE bmdma_prepare_buf (Peter)
> - Improve OpenGL and related display error messages (Peter)
> - Set PCI base address register write mask on GC64120 host bridge (Phil)
> - List PCIe Root Port and PCIe-to-PCI bridge in QEMU PCI IDs list (George)
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread