From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 1/1] tcg/ppc: Sync tcg_out_test and constraints
Date: Thu, 8 Aug 2024 11:43:00 +1000 [thread overview]
Message-ID: <20240808014300.65269-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240808014300.65269-1-richard.henderson@linaro.org>
Ensure the code structure is the same for matching constraints
and emitting code, lest we allow constants that cannot be
trivially tested.
Cc: qemu-stable@nongnu.org
Fixes: ad788aebbab ("tcg/ppc: Support TCG_COND_TST{EQ,NE}")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2487
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <44328324-af73-4439-9d2b-d414e0e13dd7@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 7f3829beeb..3553a47ba9 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -325,9 +325,11 @@ static bool tcg_target_const_match(int64_t sval, int ct,
if ((uval & ~0xffff) == 0 || (uval & ~0xffff0000ull) == 0) {
return 1;
}
- if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32
- ? mask_operand(uval, &mb, &me)
- : mask64_operand(uval << clz64(uval), &mb, &me)) {
+ if (uval == (uint32_t)uval && mask_operand(uval, &mb, &me)) {
+ return 1;
+ }
+ if (TCG_TARGET_REG_BITS == 64 &&
+ mask64_operand(uval << clz64(uval), &mb, &me)) {
return 1;
}
return 0;
@@ -1749,8 +1751,6 @@ static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg arg2,
if (type == TCG_TYPE_I32) {
arg2 = (uint32_t)arg2;
- } else if (arg2 == (uint32_t)arg2) {
- type = TCG_TYPE_I32;
}
if ((arg2 & ~0xffff) == 0) {
@@ -1761,12 +1761,11 @@ static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg arg2,
tcg_out32(s, ANDIS | SAI(arg1, dest, arg2 >> 16));
return;
}
- if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
- if (mask_operand(arg2, &mb, &me)) {
- tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc);
- return;
- }
- } else {
+ if (arg2 == (uint32_t)arg2 && mask_operand(arg2, &mb, &me)) {
+ tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc);
+ return;
+ }
+ if (TCG_TARGET_REG_BITS == 64) {
int sh = clz64(arg2);
if (mask64_operand(arg2 << sh, &mb, &me)) {
tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc);
--
2.43.0
next prev parent reply other threads:[~2024-08-08 1:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-08 1:42 [PULL 0/1] tcg patch queue Richard Henderson
2024-08-08 1:43 ` Richard Henderson [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-08-07 23:06 Richard Henderson
2024-08-07 23:06 ` [PULL 1/1] tcg/ppc: Sync tcg_out_test and constraints Richard Henderson
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