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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bd196a7ae8sm2871494a12.54.2024.08.13.03.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 03:23:42 -0700 (PDT) Date: Tue, 13 Aug 2024 12:23:41 +0200 From: Andrew Jones To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Richard Henderson , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, zong.li@sifive.com, liwei1518@gmail.com, cwshu@andestech.com, dbarboza@ventanamicro.com Subject: Re: [PATCH] target/riscv32: Fix masking of physical address Message-ID: <20240813-94c16c9efc943fe891ba7724@orel> References: <20240813071355.310710-2-ajones@ventanamicro.com> <20240813-e2c6dc0e68f76be576c72996@orel> <3f1accd0-33b8-4656-944f-f6637ee315b9@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3f1accd0-33b8-4656-944f-f6637ee315b9@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Aug 13, 2024 at 10:21:13AM GMT, Philippe Mathieu-Daudé wrote: > On 13/8/24 10:00, Andrew Jones wrote: > > On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote: > > > On 8/13/24 17:13, Andrew Jones wrote: > > > > C doesn't extend the sign bit for unsigned types since there isn't a > > > > sign bit to extend. This means a promotion of a u32 to a u64 results > > > > in the upper 32 bits of the u64 being zero. If that result is then > > > > used as a mask on another u64 the upper 32 bits will be cleared. rv32 > > > > physical addresses may be up to 34 bits wide, so we don't want to > > > > clear the high bits while page aligning the address. The fix is to > > > > revert to using target_long, since a signed type will get extended. > > > > > > > > Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP entries.") > > > > Signed-off-by: Andrew Jones > > > > --- > > > > target/riscv/cpu_helper.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > > > index 395a1d914061..dfef1b20d1e8 100644 > > > > --- a/target/riscv/cpu_helper.c > > > > +++ b/target/riscv/cpu_helper.c > > > > @@ -1323,7 +1323,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > > > > int ret = TRANSLATE_FAIL; > > > > int mode = mmuidx_priv(mmu_idx); > > > > /* default TLB page size */ > > > > - target_ulong tlb_size = TARGET_PAGE_SIZE; > > > > + target_long tlb_size = TARGET_PAGE_SIZE; > > > > > > If rv32 physical addresses are 34 bits, then you probably didn't want target_*long at all. > > > > Yes, just using hwaddr for everything that only touches physical addresses > > would probably be best, but, ifaict, it's pretty common to use target_long > > for masks used on both virtual and physical addresses (TARGET_PAGE_MASK, > > for example). This 'tlb_size' variable is used on both as well. > > Then maybe you want vaddr ("exec/vaddr.h"): > > /** > * vaddr: > * Type wide enough to contain any #target_ulong virtual address. > */ > I think hwaddr would fit better in this case since riscv32 virtual addresses are 32-bit, but I see vaddr is a u64, so it would work too. I personally don't mind changing the type of tlb_size to hwaddr, but I went with target_long in this patch since that's what it was originally and masking with a signed long mask appears to be a common pattern in QEMU. Thanks, drew