[PATCH v3 5/6] target/sparc: Implement STDFQ

[Richard Henderson <richard.henderson@linaro.org>]

Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c  | 24 +++++++++++++++++++++++-
 target/sparc/insns.decode |  4 ++--
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index eb0158a11d..6d4c0e79c9 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4531,17 +4531,39 @@ TRANS(STQFA, 64, do_st_fpr, a, MO_128)
 
 static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
 {
+    TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
+
     if (!avail_32(dc)) {
         return false;
     }
+    if (addr == NULL) {
+        return false;
+    }
     if (!supervisor(dc)) {
         return raise_priv(dc);
     }
+#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
     if (gen_trap_ifnofpu(dc)) {
         return true;
     }
-    gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
+    if (dc->fsr_qne) {
+        TCGv_i64 fq = tcg_temp_new_i64();
+
+        /* Store the single element from the queue. */
+        tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d));
+        tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4);
+
+        /* Mark the queue empty, transitioning to fp_execute state. */
+        tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,
+                       offsetof(CPUSPARCState, fsr_qne));
+        dc->fsr_qne = 0;
+    } else {
+        gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
+    }
     return true;
+#else
+    qemu_build_not_reached();
+#endif
 }
 
 static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index fbcb4f7aef..923f348580 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -644,8 +644,8 @@ STF         11 ..... 100100 ..... . .............          @r_r_ri_na
 STFSR       11 00000 100101 ..... . .............          @n_r_ri
 STXFSR      11 00001 100101 ..... . .............          @n_r_ri
 {
-  STQF      11 ..... 100110 ..... . .............          @q_r_ri_na
-  STDFQ     11 ----- 100110 ----- - -------------
+  STQF      11 ..... 100110 ..... . .............          @q_r_ri_na # v9
+  STDFQ     11 ..... 100110 ..... . .............          @r_r_ri    # v7,v8
 }
 STDF        11 ..... 100111 ..... . .............          @d_r_ri_na
 
-- 
2.43.0