From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Corbin <mark@dibsco.co.uk>, Warner Losh <imp@bsdimp.com>,
Ajeet Singh <itachis@FreeBSD.org>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants
Date: Sat, 17 Aug 2024 03:09:45 +1000 [thread overview]
Message-ID: <20240816170949.238511-14-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240816170949.238511-1-itachis@FreeBSD.org>
From: Mark Corbin <mark@dibsco.co.uk>
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_signal.h | 75 +++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_signal.h
diff --git a/bsd-user/riscv/target_arch_signal.h b/bsd-user/riscv/target_arch_signal.h
new file mode 100644
index 0000000000..1a634b865b
--- /dev/null
+++ b/bsd-user/riscv/target_arch_signal.h
@@ -0,0 +1,75 @@
+/*
+ * RISC-V signal definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGNAL_H
+#define TARGET_ARCH_SIGNAL_H
+
+#include "cpu.h"
+
+
+#define TARGET_INSN_SIZE 4 /* riscv instruction size */
+
+/* Size of the signal trampoline code placed on the stack. */
+#define TARGET_SZSIGCODE ((abi_ulong)(7 * TARGET_INSN_SIZE))
+
+/* Compare with riscv/include/_limits.h */
+#define TARGET_MINSIGSTKSZ (1024 * 4)
+#define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768)
+
+struct target_gpregs {
+ uint64_t gp_ra;
+ uint64_t gp_sp;
+ uint64_t gp_gp;
+ uint64_t gp_tp;
+ uint64_t gp_t[7];
+ uint64_t gp_s[12];
+ uint64_t gp_a[8];
+ uint64_t gp_sepc;
+ uint64_t gp_sstatus;
+};
+
+struct target_fpregs {
+ uint64_t fp_x[32][2];
+ uint64_t fp_fcsr;
+ uint32_t fp_flags;
+ uint32_t pad;
+};
+
+typedef struct target_mcontext {
+ struct target_gpregs mc_gpregs;
+ struct target_fpregs mc_fpregs;
+ uint32_t mc_flags;
+#define TARGET_MC_FP_VALID 0x01
+ uint32_t mc_pad;
+ uint64_t mc_spare[8];
+} target_mcontext_t;
+
+#define TARGET_MCONTEXT_SIZE 864
+#define TARGET_UCONTEXT_SIZE 936
+
+#include "target_os_ucontext.h"
+
+struct target_sigframe {
+ target_ucontext_t sf_uc; /* = *sf_uncontext */
+ target_siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case)*/
+};
+
+#define TARGET_SIGSTACK_ALIGN 16
+
+#endif /* TARGET_ARCH_SIGNAL_H */
--
2.34.1
next prev parent reply other threads:[~2024-08-16 17:12 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 17:09 [PATCH v2 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-19 2:57 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-19 3:06 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-19 3:08 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-16 17:09 ` Ajeet Singh [this message]
2024-08-16 17:09 ` [PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
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