From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Corbin <mark@dibsco.co.uk>, Warner Losh <imp@bsdimp.com>,
Ajeet Singh <itachis@FreeBSD.org>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions
Date: Sat, 17 Aug 2024 03:09:35 +1000 [thread overview]
Message-ID: <20240816170949.238511-4-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240816170949.238511-1-itachis@FreeBSD.org>
From: Mark Corbin <mark@dibsco.co.uk>
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index 5b436b2ac9..bdb527573b 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -130,4 +130,18 @@ static inline void target_cpu_loop(CPURISCVState *env)
}
}
+static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->gpr[xSP] = newsp;
+ }
+
+ env->gpr[xA0] = 0; /* a0 */
+ env->gpr[xT0] = 0; /* t0 */
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
#endif /* TARGET_ARCH_CPU_H */
--
2.34.1
next prev parent reply other threads:[~2024-08-16 17:10 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 17:09 [PATCH v2 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-19 2:57 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-16 17:09 ` Ajeet Singh [this message]
2024-08-16 17:09 ` [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-19 3:06 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-19 3:08 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
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