From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Corbin <mark@dibsco.co.uk>, Warner Losh <imp@bsdimp.com>,
Ajeet Singh <itachis@FreeBSD.org>,
Kyle Evans <kevans@FreeBSD.org>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection
Date: Sat, 17 Aug 2024 03:09:37 +1000 [thread overview]
Message-ID: <20240816170949.238511-6-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240816170949.238511-1-itachis@FreeBSD.org>
From: Mark Corbin <mark@dibsco.co.uk>
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_elf.h
diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h
new file mode 100644
index 0000000000..4eb915e61e
--- /dev/null
+++ b/bsd-user/riscv/target_arch_elf.h
@@ -0,0 +1,42 @@
+/*
+ * RISC-V ELF definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_ELF_H
+#define TARGET_ARCH_ELF_H
+
+#define elf_check_arch(x) ((x) == EM_RISCV)
+#define ELF_START_MMAP 0x80000000
+#define ELF_ET_DYN_LOAD_ADDR 0x100000
+#define ELF_CLASS ELFCLASS64
+
+#define ELF_DATA ELFDATA2LSB
+#define ELF_ARCH EM_RISCV
+
+#define ELF_HWCAP get_elf_hwcap()
+static uint32_t get_elf_hwcap(void)
+{
+ RISCVCPU *cpu = RISCV_CPU(thread_cpu);
+
+ return cpu->env.misa_ext_mask;
+}
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+#endif /* TARGET_ARCH_ELF_H */
--
2.34.1
next prev parent reply other threads:[~2024-08-16 17:12 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 17:09 [PATCH v2 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-19 2:57 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-16 17:09 ` Ajeet Singh [this message]
2024-08-16 17:09 ` [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-19 3:06 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-19 3:08 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
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