From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Waldemar Brodkorb" <wbx@uclibc-ng.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 05/20] target/mips: Use correct MMU index in get_pte()
Date: Tue, 20 Aug 2024 00:51:01 +0200 [thread overview]
Message-ID: <20240819225116.17928-6-philmd@linaro.org> (raw)
In-Reply-To: <20240819225116.17928-1-philmd@linaro.org>
When refactoring page_table_walk_refill() in commit 4e999bf419
we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill()
-> get_pte()
-> cpu_ld[lq]_code()
-> cpu_mmu_index()
Since we don't mask anymore the modes in hflags, cpu_mmu_index()
can return UM or SM, while we only expect KM or ERL.
Fix by propagating ptw_mmu_idx to get_pte(), and use the
cpu_ld/st_code_mmu() API with the correct MemOpIdx.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Reported-by: Waldemar Brodkorb <wbx@uclibc-ng.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2470
Fixes: 4e999bf419 ("target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240814090452.2591-3-philmd@linaro.org>
---
target/mips/tcg/sysemu/tlb_helper.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 60147ba0af..0e94e00a5f 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -593,16 +593,21 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
*/
static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op,
- uint64_t *pte)
+ uint64_t *pte, unsigned ptw_mmu_idx)
{
+ MemOpIdx oi;
+
if ((vaddr & (memop_size(op) - 1)) != 0) {
return false;
}
+
+ oi = make_memop_idx(op | MO_TE, ptw_mmu_idx);
if (op == MO_64) {
- *pte = cpu_ldq_code(env, vaddr);
+ *pte = cpu_ldq_code_mmu(env, vaddr, oi, 0);
} else {
- *pte = cpu_ldl_code(env, vaddr);
+ *pte = cpu_ldl_code_mmu(env, vaddr, oi, 0);
}
+
return true;
}
@@ -642,7 +647,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
/* wrong base address */
return 0;
}
- if (!get_pte(env, *vaddr, directory_mop, &entry)) {
+ if (!get_pte(env, *vaddr, directory_mop, &entry, ptw_mmu_idx)) {
return 0;
}
@@ -668,7 +673,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
ptw_mmu_idx) != TLBRET_MATCH) {
return 0;
}
- if (!get_pte(env, vaddr2, leaf_mop, &entry)) {
+ if (!get_pte(env, vaddr2, leaf_mop, &entry, ptw_mmu_idx)) {
return 0;
}
entry = get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew);
@@ -823,7 +828,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
ptw_mmu_idx) != TLBRET_MATCH) {
return false;
}
- if (!get_pte(env, vaddr, leaf_mop, &dir_entry)) {
+ if (!get_pte(env, vaddr, leaf_mop, &dir_entry, ptw_mmu_idx)) {
return false;
}
dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew);
@@ -835,7 +840,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
ptw_mmu_idx) != TLBRET_MATCH) {
return false;
}
- if (!get_pte(env, vaddr, leaf_mop, &dir_entry)) {
+ if (!get_pte(env, vaddr, leaf_mop, &dir_entry, ptw_mmu_idx)) {
return false;
}
dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew);
--
2.45.2
next prev parent reply other threads:[~2024-08-19 22:55 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-19 22:50 [PULL 00/20] Misc fixes for 2024-08-20 Philippe Mathieu-Daudé
2024-08-19 22:50 ` [PULL 01/20] hw/mips/loongson3_virt: Store core_iocsr into LoongsonMachineState Philippe Mathieu-Daudé
2024-08-19 22:50 ` [PULL 02/20] hw/mips/loongson3_virt: Fix condition of IPI IOCSR connection Philippe Mathieu-Daudé
2024-08-19 22:50 ` [PULL 03/20] qemu-options.hx: correct formatting -smbios type=4 Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 04/20] target/mips: Pass page table entry size as MemOp to get_pte() Philippe Mathieu-Daudé
2024-08-19 22:51 ` Philippe Mathieu-Daudé [this message]
2024-08-19 22:51 ` [PULL 06/20] target/mips: Load PTE as DATA Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 07/20] hw/dma/xilinx_axidma: Use semicolon at end of statement, not comma Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 08/20] hw/remote/message.c: Don't directly invoke DeviceClass:reset Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 09/20] linux-user/mips: Do not try to use removed R5900 CPU Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 10/20] linux-user/mips: Select Octeon68XX CPU for Octeon binaries Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 11/20] linux-user/mips: Select MIPS64R2-generic for Rel2 binaries Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 12/20] linux-user/mips: Select Loongson CPU for Loongson binaries Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 13/20] tests/avocado: exec_command should not consume console output Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 14/20] tests/avocado: Mark ppc_hv_tests.py as non-flaky after fixed console interaction Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 15/20] contrib/plugins/execlog: Fix shadowed declaration warning Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 16/20] target/sparc: Restrict STQF to sparcv9 Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 17/20] hw/ppc/Kconfig: Add missing SERIAL_ISA dependency to POWERNV machine Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 18/20] hw/i386/pc: Unify vmport=auto handling Philippe Mathieu-Daudé
2024-08-20 19:48 ` Philippe Mathieu-Daudé
2024-08-20 20:32 ` Kamil Szczęk
2024-08-20 22:45 ` Richard Henderson
2024-08-20 22:55 ` Kamil Szczęk
2024-08-19 22:51 ` [PULL 19/20] hw/i386/pc: Ensure vmport prerequisites are fulfilled Philippe Mathieu-Daudé
2024-08-19 22:51 ` [PULL 20/20] crypto/tlscredspsk: Free username on finalize Philippe Mathieu-Daudé
2024-08-20 6:50 ` [PULL 00/20] Misc fixes for 2024-08-20 Richard Henderson
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