From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com,
Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v5 15/15] disas/riscv: enable disassembly for compressed sspush/sspopchk
Date: Mon, 19 Aug 2024 17:01:29 -0700 [thread overview]
Message-ID: <20240820000129.3522346-16-debug@rivosinc.com> (raw)
In-Reply-To: <20240820000129.3522346-1-debug@rivosinc.com>
sspush and sspopchk have equivalent compressed encoding taken from zcmop.
cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding
for both rs1 and rs2 from space bitfield, this required a new codec.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
disas/riscv.c | 19 ++++++++++++++++++-
disas/riscv.h | 1 +
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index f1f4ffc50a..8eeaa9f843 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -980,6 +980,8 @@ typedef enum {
rv_op_ssrdp = 949,
rv_op_ssamoswap_w = 950,
rv_op_ssamoswap_d = 951,
+ rv_op_c_sspush = 952,
+ rv_op_c_sspopchk = 953,
} rv_op;
/* register names */
@@ -2244,6 +2246,10 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
{ "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
+ rv_op_sspush, 0 },
+ { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
+ rv_op_sspopchk, 0 },
};
/* CSR names */
@@ -2604,7 +2610,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
if (dec->cfg->ext_zcmop) {
if ((((inst >> 2) & 0b111111) == 0b100000) &&
(((inst >> 11) & 0b11) == 0b0)) {
- op = rv_c_mop_1 + ((inst >> 8) & 0b111);
+ unsigned int cmop_code = 0;
+ cmop_code = ((inst >> 8) & 0b111);
+ op = rv_c_mop_1 + cmop_code;
+ if (dec->cfg->ext_zicfiss) {
+ op = (cmop_code == 0) ? rv_op_c_sspush : op;
+ op = (cmop_code == 2) ? rv_op_c_sspopchk : op;
+ }
break;
}
}
@@ -4923,6 +4935,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
case rv_codec_lp:
dec->imm = operand_lpl(inst);
break;
+ case rv_codec_cmop_ss:
+ dec->rd = rv_ireg_zero;
+ dec->rs1 = dec->rs2 = operand_crs1(inst);
+ dec->imm = 0;
+ break;
};
}
diff --git a/disas/riscv.h b/disas/riscv.h
index 4895c5a301..6a3b371cd3 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -167,6 +167,7 @@ typedef enum {
rv_codec_r2_imm2_imm5,
rv_codec_fli,
rv_codec_lp,
+ rv_codec_cmop_ss,
} rv_codec;
/* structures */
--
2.44.0
prev parent reply other threads:[~2024-08-20 0:06 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-20 0:01 [PATCH v5 00/15] riscv support for control flow integrity extensions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 01/15] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 02/15] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-20 5:17 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 03/15] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 04/15] target/riscv: additional code information for sw check Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 05/15] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-20 5:24 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 06/15] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-20 5:29 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 07/15] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 08/15] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 09/15] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-20 5:34 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 10/15] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 11/15] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-20 7:35 ` Deepak Gupta
2024-08-20 9:20 ` Richard Henderson
2024-08-20 18:55 ` Deepak Gupta
2024-08-20 19:45 ` Deepak Gupta
2024-08-20 22:33 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 12/15] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 13/15] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 14/15] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-20 0:01 ` Deepak Gupta [this message]
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