From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu,
bmeng.cn@gmail.com, liwei1518@gmail.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com,
Deepak Gupta <debug@rivosinc.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well
Date: Tue, 27 Aug 2024 16:18:45 -0700 [thread overview]
Message-ID: <20240827231906.553327-2-debug@rivosinc.com> (raw)
In-Reply-To: <20240827231906.553327-1-debug@rivosinc.com>
Execution environment config CSR controlling user env and current
privilege state shouldn't be limited to qemu-system only. *envcfg
CSRs control enabling of features in next lesser mode. In some cases
bits *envcfg CSR can be lit up by kernel as part of kernel policy or
software (user app) can choose to opt-in by issuing a system call
(e.g. prctl). In case of qemu-user, it should be no different because
qemu is providing underlying execution environment facility and thus
either should provide some default value in *envcfg CSRs or react to
system calls (prctls) initiated from application.
`henvcfg` has been left for qemu-system only because it is not expected
that someone will use qemu-user where application is expected to have
hypervisor underneath which is controlling its execution environment. If
such a need arises then `henvcfg` could be exposed as well.
Relevant discussion:
https://lore.kernel.org/all/CAKmqyKOTVWPFep2msTQVdUmJErkH+bqCcKEQ4hAnyDFPdWKe0Q@mail.gmail.com/
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87742047ce..270a2a031c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -226,8 +226,12 @@ struct CPUArchState {
uint32_t elf_flags;
#endif
-#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* CSRs for execution environment configuration */
+ uint64_t menvcfg;
+ target_ulong senvcfg;
+
+#ifndef CONFIG_USER_ONLY
/* This contains QEMU specific information about the virt state. */
bool virt_enabled;
target_ulong geilen;
@@ -429,12 +433,9 @@ struct CPUArchState {
target_ulong upmmask;
target_ulong upmbase;
- /* CSRs for execution environment configuration */
- uint64_t menvcfg;
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
- target_ulong senvcfg;
uint64_t henvcfg;
#endif
target_ulong cur_pmmask;
--
2.44.0
next prev parent reply other threads:[~2024-08-27 23:22 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-27 23:18 [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-27 23:18 ` Deepak Gupta [this message]
2024-08-28 0:04 ` [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well Alistair Francis
2024-08-27 23:18 ` [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg Deepak Gupta
2024-08-28 0:10 ` Alistair Francis
2024-08-28 0:16 ` Deepak Gupta
2024-08-28 11:36 ` Richard Henderson
2024-08-27 23:18 ` [PATCH v10 03/21] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-27 23:59 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 05/21] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 06/21] target/riscv: additional code information for sw check Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-28 0:02 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 11/21] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-28 0:00 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 12/21] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 14/21] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 15/21] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 16/21] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 17/21] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 19/21] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 21/21] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
2024-08-27 23:22 ` [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-28 0:02 ` Alistair Francis
2024-08-28 0:04 ` Deepak Gupta
2024-08-28 0:11 ` Alistair Francis
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