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From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu,
	bmeng.cn@gmail.com, liwei1518@gmail.com,
	dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
	jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com,
	Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v10 03/21] target/riscv: Add zicfilp extension
Date: Tue, 27 Aug 2024 16:18:47 -0700	[thread overview]
Message-ID: <20240827231906.553327-4-debug@rivosinc.com> (raw)
In-Reply-To: <20240827231906.553327-1-debug@rivosinc.com>

zicfilp [1] riscv cpu extension enables forward control flow integrity.
If enabled, all indirect calls must land on a landing pad instruction.

This patch sets up space for zicfilp extension in cpuconfig. zicfilp
is dependend on zicsr.

[1] - https://github.com/riscv/riscv-cfi

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
---
 target/riscv/cpu.c         | 1 +
 target/riscv/cpu_cfg.h     | 1 +
 target/riscv/tcg/tcg-cpu.c | 5 +++++
 3 files changed, 7 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 33ef4eb795..43156ebb92 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -106,6 +106,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11),
     ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11),
     ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11),
+    ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
     ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 120905a254..88d5defbb5 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -67,6 +67,7 @@ struct RISCVCPUConfig {
     bool ext_zicbom;
     bool ext_zicbop;
     bool ext_zicboz;
+    bool ext_zicfilp;
     bool ext_zicond;
     bool ext_zihintntl;
     bool ext_zihintpause;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b8814ab753..ed19586c9d 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -623,6 +623,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu->pmu_avail_ctrs = 0;
     }
 
+    if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) {
+        error_setg(errp, "zicfilp extension requires zicsr extension");
+        return;
+    }
+
     /*
      * Disable isa extensions based on priv spec after we
      * validated and set everything we need.
-- 
2.44.0



  parent reply	other threads:[~2024-08-27 23:22 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-27 23:18 [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-28  0:04   ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg Deepak Gupta
2024-08-28  0:10   ` Alistair Francis
2024-08-28  0:16     ` Deepak Gupta
2024-08-28 11:36       ` Richard Henderson
2024-08-27 23:18 ` Deepak Gupta [this message]
2024-08-27 23:59   ` [PATCH v10 03/21] target/riscv: Add zicfilp extension Alistair Francis
2024-08-27 23:18 ` [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 05/21] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 06/21] target/riscv: additional code information for sw check Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-28  0:02   ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 11/21] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-28  0:00   ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 12/21] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 14/21] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 15/21] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 16/21] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 17/21] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 19/21] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 21/21] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
2024-08-27 23:22 ` [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-28  0:02 ` Alistair Francis
2024-08-28  0:04   ` Deepak Gupta
2024-08-28  0:11     ` Alistair Francis

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