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From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Corbin <mark@dibsco.co.uk>, Warner Losh <imp@bsdimp.com>,
	Ajeet Singh <itachis@FreeBSD.org>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v4 14/17] bsd-user: Implement RISC-V signal trampoline setup functions
Date: Wed, 28 Aug 2024 19:52:40 +1000	[thread overview]
Message-ID: <20240828095243.90491-15-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240828095243.90491-1-itachis@FreeBSD.org>

From: Mark Corbin <mark@dibsco.co.uk>

Added functions for setting up the RISC-V signal trampoline and signal
frame:

'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal handler
address, and the signal frame pointer.

'setup_sigframe_arch()': Initializes the signal frame with the current
machine context.This function copies the context from the CPU state to
the signal frame, preparing it for the signal handler.

Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 bsd-user/riscv/signal.c | 63 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 bsd-user/riscv/signal.c

diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c
new file mode 100644
index 0000000000..2597fec2fd
--- /dev/null
+++ b/bsd-user/riscv/signal.c
@@ -0,0 +1,63 @@
+/*
+ *  RISC-V signal definitions
+ *
+ *  Copyright (c) 2019 Mark Corbin
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "qemu.h"
+
+/*
+ * Compare with sendsig() in riscv/riscv/exec_machdep.c
+ * Assumes that target stack frame memory is locked.
+ */
+abi_long
+set_sigtramp_args(CPURISCVState *regs, int sig, struct target_sigframe *frame,
+    abi_ulong frame_addr, struct target_sigaction *ka)
+{
+    /*
+     * Arguments to signal handler:
+     *  a0 (10) = signal number
+     *  a1 (11) = siginfo pointer
+     *  a2 (12) = ucontext pointer
+     *  pc      = signal pointer handler
+     *  sp (2)  = sigframe pointer
+     *  ra (1)  = sigtramp at base of user stack
+     */
+
+     regs->gpr[xA0] = sig;
+     regs->gpr[xA1] = frame_addr +
+         offsetof(struct target_sigframe, sf_si);
+     regs->gpr[xA2] = frame_addr +
+         offsetof(struct target_sigframe, sf_uc);
+     regs->pc = ka->_sa_handler;
+     regs->gpr[xSP] = frame_addr;
+     regs->gpr[xRA] = TARGET_PS_STRINGS - TARGET_SZSIGCODE;
+     return 0;
+}
+
+/*
+ * Compare to riscv/riscv/exec_machdep.c sendsig()
+ * Assumes that the memory is locked if frame points to user memory.
+ */
+abi_long setup_sigframe_arch(CPURISCVState *env, abi_ulong frame_addr,
+                             struct target_sigframe *frame, int flags)
+{
+    target_mcontext_t *mcp = &frame->sf_uc.uc_mcontext;
+
+    get_mcontext(env, mcp, flags);
+    return 0;
+}
-- 
2.34.1



  parent reply	other threads:[~2024-08-28  9:54 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-28  9:52 [PATCH v4 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-09-06  0:25   ` Alistair Francis
2024-08-28  9:52 ` [PATCH v4 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-28  9:52 ` Ajeet Singh [this message]
2024-08-28  9:52 ` [PATCH v4 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-28  9:52 ` [PATCH v4 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh

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