From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com,
Deepak Gupta <debug@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v12 20/20] target/riscv: Expose zicfiss extension as a cpu property
Date: Thu, 29 Aug 2024 16:34:24 -0700 [thread overview]
Message-ID: <20240829233425.1005029-21-debug@rivosinc.com> (raw)
In-Reply-To: <20240829233425.1005029-1-debug@rivosinc.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c5ebcefeb5..2592465e24 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1485,6 +1485,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
+ MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false),
MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
--
2.44.0
prev parent reply other threads:[~2024-08-29 23:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 23:34 [PATCH v12 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-30 2:10 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-30 2:13 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-30 5:20 ` Richard Henderson
2024-08-30 5:56 ` Deepak Gupta
2024-08-30 16:30 ` Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 17/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 18/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-29 23:34 ` Deepak Gupta [this message]
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