From: Alireza Sanaee via <qemu-devel@nongnu.org>
To: Zhao Liu <zhao1.liu@intel.com>
Cc: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,
<zhenyu.z.wang@intel.com>, <dapeng1.mi@linux.intel.com>,
<yongwei.ma@intel.com>, <armbru@redhat.com>,
<farman@linux.ibm.com>, <peter.maydell@linaro.org>,
<mst@redhat.com>, <anisinha@redhat.com>,
<shannon.zhaosl@gmail.com>, <imammedo@redhat.com>,
<mtosatti@redhat.com>, <berrange@redhat.com>,
<richard.henderson@linaro.org>, <linuxarm@huwei.com>,
<shameerali.kolothum.thodi@huawei.com>,
<Jonathan.Cameron@huawei.com>, <jiangkunkun@huawei.com>
Subject: Re: [RFC PATCH 0/2] Specifying cache topology on ARM
Date: Mon, 2 Sep 2024 11:25:19 +0100 [thread overview]
Message-ID: <20240902112519.00005b67@huawei.com> (raw)
In-Reply-To: <ZtL9u9kQcx0GtEKq@intel.com>
On Sat, 31 Aug 2024 19:25:47 +0800
Zhao Liu <zhao1.liu@intel.com> wrote:
> Hi Alireza,
>
> Great to see your Arm side implementation!
>
> On Fri, Aug 23, 2024 at 01:54:44PM +0100, Alireza Sanaee wrote:
> > Date: Fri, 23 Aug 2024 13:54:44 +0100
> > From: Alireza Sanaee <alireza.sanaee@huawei.com>
> > Subject: [RFC PATCH 0/2] Specifying cache topology on ARM
> > X-Mailer: git-send-email 2.34.1
> >
>
> [snip]
>
> >
> > The following command will represent the system.
> >
> > ./qemu-system-aarch64 \
> > -machine virt,**smp-cache=cache0** \
> > -cpu max \
> > -m 2048 \
> > -smp sockets=2,clusters=1,cores=2,threads=2 \
> > -kernel ./Image.gz \
> > -append "console=ttyAMA0 root=/dev/ram rdinit=/init acpi=force" \
> > -initrd rootfs.cpio.gz \
> > -bios ./edk2-aarch64-code.fd \
> > **-object
> > '{"qom-type":"smp-cache","id":"cache0","caches":[{"name":"l1d","topo":"core"},{"name":"l1i","topo":"core"},{"name":"l2","topo":"cluster"},{"name":"l3","topo":"socket"}]}'**
> > \ -nographic
>
> I plan to refresh a new version soon, in which the smp-cache array
> will be integrated into -machine totally. And I'cc you then.
>
> Regards,
> Zhao
>
>
Hi Zhao,
Yes, please keep me CCed.
One thing that I noticed, sometimes, since you were going down the
Intel path, some variables couldn't be NULL. But when I was gonna go
down to ARM path, I faced some scenarios where I ended up with
some uninit vars which is still OK but could have been avoided.
Looking forward to the next revision.
Alireza
next prev parent reply other threads:[~2024-09-02 10:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-23 12:54 [RFC PATCH 0/2] Specifying cache topology on ARM Alireza Sanaee via
2024-08-23 12:54 ` [PATCH 1/2] target/arm/tcg: increase cache level for cpu=max Alireza Sanaee via
2024-08-23 12:54 ` [PATCH 2/2] hw/acpi: add cache hierarchy node to pptt table Alireza Sanaee via
2024-08-31 11:47 ` Zhao Liu
2024-08-31 11:25 ` [RFC PATCH 0/2] Specifying cache topology on ARM Zhao Liu
2024-09-02 10:25 ` Alireza Sanaee via [this message]
2024-09-02 12:23 ` Zhao Liu
2024-09-02 11:49 ` Marcin Juszkiewicz
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