[PATCH v4 0/2] target/loongarch: Add loongson binary translation feature

[PATCH v4 0/2] target/loongarch: Add loongson binary translation feature

[Bibo Mao]

Loongson Binary Translation (LBT) is used to accelerate binary
translation. LBT feature is added in kvm mode, not supported in TCG
mode since it is not emulated.

Here lbt=on/off property is added to parse command line to
enable/disable lbt feature. Also fix registers relative lbt are saved
and restored during migration.

---
v3 ... v4:
  1. Verify and enable LBT feature in function kvm_arch_init_vcpu()
     rather than loongarch_cpu_post_init(), since LBT feature is only
     effective in kvm mode and function kvm_feature_supported() can be
     defined as static.
  2. Define structure elment ftop in structure LoongArchBT as uint32_t
     to keep consist with kernel and real HW.

v2 ... v3:
  1. Property lbt is added only if kvm is enabled
  2. Use feature variable lbt with OnOffAuto type, rather than feature
     bitmap flags default_features and forced_features

v1 ... v2:
  1. Add LBT register saving and restoring in vmstate
  2. Add two pseudo feature flags: default_features and forced_features
---
Bibo Mao (2):
  target/loongarch: Add loongson binary translation feature
  target/loongarch: Implement lbt registers save/restore function

 target/loongarch/cpu.c                |  24 ++++++
 target/loongarch/cpu.h                |  18 ++++
 target/loongarch/kvm/kvm.c            | 117 +++++++++++++++++++++++++-
 target/loongarch/loongarch-qmp-cmds.c |   2 +-
 target/loongarch/machine.c            |  24 ++++++
 5 files changed, 183 insertions(+), 2 deletions(-)


base-commit: e638d685ec2a0700fb9529cbd1b2823ac4120c53
-- 
2.39.3

[PATCH v4 1/2] target/loongarch: Add loongson binary translation feature

[Bibo Mao]

Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).

Now LBT feature is added in kvm mode, not supported in TCG mode since
it is not emulated. Feature variable lbt is added with OnOffAuto type,
If lbt feature is not supported with KVM host, it reports error if there
is lbt=on command line.

If there is no any command line about lbt parameter, it checks whether
KVM host supports lbt feature and set the corresponding value in cpucfg.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c                | 24 +++++++++++
 target/loongarch/cpu.h                |  6 +++
 target/loongarch/kvm/kvm.c            | 57 ++++++++++++++++++++++++++-
 target/loongarch/loongarch-qmp-cmds.c |  2 +-
 4 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 5e85b9dbef..42a575e5e3 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -650,12 +650,36 @@ static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
     }
 }
 
+static bool loongarch_get_lbt(Object *obj, Error **errp)
+{
+    return LOONGARCH_CPU(obj)->lbt != ON_OFF_AUTO_OFF;
+}
+
+static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+
+    cpu->lbt = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+}
+
 void loongarch_cpu_post_init(Object *obj)
 {
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+
     object_property_add_bool(obj, "lsx", loongarch_get_lsx,
                              loongarch_set_lsx);
     object_property_add_bool(obj, "lasx", loongarch_get_lasx,
                              loongarch_set_lasx);
+    /* lbt is enabled only in kvm mode, not supported in tcg mode */
+    if (kvm_enabled()) {
+        cpu->lbt = ON_OFF_AUTO_AUTO;
+        object_property_add_bool(obj, "lbt", loongarch_get_lbt,
+                                 loongarch_set_lbt);
+        object_property_set_description(obj, "lbt",
+                                   "Set off to disable Binary Tranlation.");
+    } else {
+        cpu->lbt = ON_OFF_AUTO_OFF;
+    }
 }
 
 static void loongarch_cpu_init(Object *obj)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 6c41fafb70..2b3f2758f6 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -153,6 +153,7 @@ FIELD(CPUCFG2, LLFTP_VER, 15, 3)
 FIELD(CPUCFG2, LBT_X86, 18, 1)
 FIELD(CPUCFG2, LBT_ARM, 19, 1)
 FIELD(CPUCFG2, LBT_MIPS, 20, 1)
+FIELD(CPUCFG2, LBT_ALL, 18, 3)
 FIELD(CPUCFG2, LSPW, 21, 1)
 FIELD(CPUCFG2, LAM, 22, 1)
 
@@ -281,6 +282,10 @@ struct LoongArchTLB {
 typedef struct LoongArchTLB LoongArchTLB;
 #endif
 
+enum loongarch_features {
+    LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
+};
+
 typedef struct CPUArchState {
     uint64_t gpr[32];
     uint64_t pc;
@@ -381,6 +386,7 @@ struct ArchCPU {
     CPULoongArchState env;
     QEMUTimer timer;
     uint32_t  phy_id;
+    OnOffAuto lbt;
 
     /* 'compatible' string for this CPU for Linux device trees */
     const char *dtb_compatible;
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index e1be6a6959..ca56694a81 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -9,6 +9,7 @@
 #include <sys/ioctl.h>
 #include <linux/kvm.h>
 
+#include "qapi/error.h"
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 #include "qemu/main-loop.h"
@@ -663,17 +664,71 @@ static void kvm_loongarch_vm_stage_change(void *opaque, bool running,
     }
 }
 
+static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
+{
+    int ret;
+    struct kvm_device_attr attr;
+
+    switch (feature) {
+    case LOONGARCH_FEATURE_LBT:
+        /*
+         * Return all if all the LBT features are supported such as:
+         *  KVM_LOONGARCH_VM_FEAT_X86BT
+         *  KVM_LOONGARCH_VM_FEAT_ARMBT
+         *  KVM_LOONGARCH_VM_FEAT_MIPSBT
+         */
+        attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
+        attr.attr = KVM_LOONGARCH_VM_FEAT_X86BT;
+        ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
+        attr.attr = KVM_LOONGARCH_VM_FEAT_ARMBT;
+        ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
+        attr.attr = KVM_LOONGARCH_VM_FEAT_MIPSBT;
+        ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
+        return (ret == 0);
+    default:
+        return false;
+    }
+}
+
+static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
+{
+    CPULoongArchState *env = cpu_env(cs);
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    bool kvm_supported;
+
+    kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LBT);
+    if (cpu->lbt == ON_OFF_AUTO_ON) {
+        if (kvm_supported) {
+            env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7);
+        } else {
+            error_setg(errp, "'lbt' feature not supported by KVM on this host");
+            return -ENOTSUP;
+        }
+    } else if ((cpu->lbt == ON_OFF_AUTO_AUTO) && kvm_supported) {
+        env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7);
+    }
+
+    return 0;
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     uint64_t val;
+    int ret;
+    Error *local_err = NULL;
 
+    ret = 0;
     qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs);
 
     if (!kvm_get_one_reg(cs, KVM_REG_LOONGARCH_DEBUG_INST, &val)) {
         brk_insn = val;
     }
 
-    return 0;
+    ret = kvm_cpu_check_lbt(cs, &local_err);
+    if (ret < 0) {
+        error_report_err(local_err);
+    }
+    return ret;
 }
 
 int kvm_arch_destroy_vcpu(CPUState *cs)
diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
index 8721a5eb13..c6f6e1ef85 100644
--- a/target/loongarch/loongarch-qmp-cmds.c
+++ b/target/loongarch/loongarch-qmp-cmds.c
@@ -40,7 +40,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static const char *cpu_model_advertised_features[] = {
-    "lsx", "lasx", NULL
+    "lsx", "lasx", "lbt", NULL
 };
 
 CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
-- 
2.39.3

Re: [PATCH v4 1/2] target/loongarch: Add loongson binary translation feature

[gaosong]

在 2024/9/4 下午2:18, Bibo Mao 写道:
> Loongson Binary Translation (LBT) is used to accelerate binary
> translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
> eflags (eflags) and x87 fpu stack pointer (ftop).
> 
> Now LBT feature is added in kvm mode, not supported in TCG mode since
> it is not emulated. Feature variable lbt is added with OnOffAuto type,
> If lbt feature is not supported with KVM host, it reports error if there
> is lbt=on command line.
> 
> If there is no any command line about lbt parameter, it checks whether
> KVM host supports lbt feature and set the corresponding value in cpucfg.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/cpu.c                | 24 +++++++++++
>   target/loongarch/cpu.h                |  6 +++
>   target/loongarch/kvm/kvm.c            | 57 ++++++++++++++++++++++++++-
>   target/loongarch/loongarch-qmp-cmds.c |  2 +-
>   4 files changed, 87 insertions(+), 2 deletions(-)
> 

Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks
Song Gao

[PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[Bibo Mao]

Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
to save/restore lbt registers.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.h     | 12 ++++++++
 target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++
 target/loongarch/machine.c | 24 +++++++++++++++
 3 files changed, 96 insertions(+)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 2b3f2758f6..0d0a5a58a8 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -286,6 +286,17 @@ enum loongarch_features {
     LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
 };
 
+typedef struct  LoongArchBT {
+    /* scratch registers */
+    uint64_t scr0;
+    uint64_t scr1;
+    uint64_t scr2;
+    uint64_t scr3;
+    /* loongarch eflags */
+    uint64_t eflags;
+    uint32_t ftop;
+} lbt_t;
+
 typedef struct CPUArchState {
     uint64_t gpr[32];
     uint64_t pc;
@@ -293,6 +304,7 @@ typedef struct CPUArchState {
     fpr_t fpr[32];
     bool cf[8];
     uint32_t fcsr0;
+    lbt_t  lbt;
 
     uint32_t cpucfg[21];
 
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index ca56694a81..ed609b9d50 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -477,6 +477,56 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs)
     return ret;
 }
 
+static int kvm_loongarch_put_lbt(CPUState *cs)
+{
+    CPULoongArchState *env = cpu_env(cs);
+    uint64_t val;
+    int ret;
+
+    /* check whether vm support LBT firstly */
+    if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) {
+        return 0;
+    }
+
+    /* set six LBT registers including scr0-scr3, eflags, ftop */
+    ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0);
+    ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1);
+    ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2);
+    ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3);
+    ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &env->lbt.eflags);
+    /*
+     * Be cautious, KVM_REG_LOONGARCH_LBT_FTOP is defined as 64-bit however
+     * lbt.ftop is 32-bit
+     */
+    val = env->lbt.ftop;
+    ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val);
+
+    return ret;
+}
+
+static int kvm_loongarch_get_lbt(CPUState *cs)
+{
+    CPULoongArchState *env = cpu_env(cs);
+    uint64_t val;
+    int ret;
+
+    /* check whether vm support LBT firstly */
+    if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) {
+        return 0;
+    }
+
+    /* get six LBT registers including scr0-scr3, eflags, ftop */
+    ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0);
+    ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1);
+    ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2);
+    ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3);
+    ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &env->lbt.eflags);
+    ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val);
+    env->lbt.ftop = (uint32_t)val;
+
+    return ret;
+}
+
 void kvm_arch_reset_vcpu(CPULoongArchState *env)
 {
     env->mp_state = KVM_MP_STATE_RUNNABLE;
@@ -610,6 +660,11 @@ int kvm_arch_get_registers(CPUState *cs)
         return ret;
     }
 
+    ret = kvm_loongarch_get_lbt(cs);
+    if (ret) {
+        return ret;
+    }
+
     ret = kvm_loongarch_get_mpstate(cs);
     return ret;
 }
@@ -638,6 +693,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
+    ret = kvm_loongarch_put_lbt(cs);
+    if (ret) {
+        return ret;
+    }
+
     ret = kvm_loongarch_put_mpstate(cs);
     return ret;
 }
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index 08a7fa5370..04f2eb8ea1 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -110,6 +110,29 @@ static const VMStateDescription vmstate_lasx = {
     },
 };
 
+static bool lbt_needed(void *opaque)
+{
+    LoongArchCPU *cpu = opaque;
+
+    return !!FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL);
+}
+
+static const VMStateDescription vmstate_lbt = {
+    .name = "cpu/lbt",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .needed = lbt_needed,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT64(env.lbt.scr0,   LoongArchCPU),
+        VMSTATE_UINT64(env.lbt.scr1,   LoongArchCPU),
+        VMSTATE_UINT64(env.lbt.scr2,   LoongArchCPU),
+        VMSTATE_UINT64(env.lbt.scr3,   LoongArchCPU),
+        VMSTATE_UINT64(env.lbt.eflags, LoongArchCPU),
+        VMSTATE_UINT32(env.lbt.ftop,   LoongArchCPU),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static bool tlb_needed(void *opaque)
 {
@@ -219,6 +242,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
         &vmstate_tlb,
 #endif
+        &vmstate_lbt,
         NULL
     }
 };
-- 
2.39.3

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[gaosong]

在 2024/9/4 下午2:18, Bibo Mao 写道:
> Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
> to save/restore lbt registers.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/cpu.h     | 12 ++++++++
>   target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++
>   target/loongarch/machine.c | 24 +++++++++++++++
>   3 files changed, 96 insertions(+)
> 

Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks
Song Gao

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[gaosong]

在 2024/9/9 下午7:52, gaosong 写道:
>
>
> 在 2024/9/4 下午2:18, Bibo Mao 写道:
>> Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
>> to save/restore lbt registers.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   target/loongarch/cpu.h     | 12 ++++++++
>>   target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++
>>   target/loongarch/machine.c | 24 +++++++++++++++
>>   3 files changed, 96 insertions(+)
>>
>
> Reviewed-by: Song Gao <gaosong@loongson.cn>
>
> Thanks
> Song Gao
Hi,  this patch need rebase.

Applying: target/loongarch: Implement lbt registers save/restore function
error: sha1 information is lacking or useless (target/loongarch/kvm/kvm.c).
error: could not build fake ancestor
Patch failed at 0001 target/loongarch: Implement lbt registers 
save/restore function


Thanks.
Song Gao.

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[maobibo]

On 2024/9/9 下午9:13, gaosong wrote:
> 在 2024/9/9 下午7:52, gaosong 写道:
>>
>>
>> 在 2024/9/4 下午2:18, Bibo Mao 写道:
>>> Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate.
>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added
>>> to save/restore lbt registers.
>>>
>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>>> ---
>>>   target/loongarch/cpu.h     | 12 ++++++++
>>>   target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++
>>>   target/loongarch/machine.c | 24 +++++++++++++++
>>>   3 files changed, 96 insertions(+)
>>>
>>
>> Reviewed-by: Song Gao <gaosong@loongson.cn>
>>
>> Thanks
>> Song Gao
> Hi,  this patch need rebase.
> 
> Applying: target/loongarch: Implement lbt registers save/restore function
> error: sha1 information is lacking or useless (target/loongarch/kvm/kvm.c).
> error: could not build fake ancestor
> Patch failed at 0001 target/loongarch: Implement lbt registers 
> save/restore function

Hi Song,

It can apply with the latest qemu version on my side, only that it fails 
to compile since kvm uapi header files need be updated.

LBT patch on qemu side can be skipped here since it depends on LBT patch 
merged on kernel side firstly.

Regards
Bibo Mao
> 
> 
> Thanks.
> Song Gao.
> 

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[gaosong]

在 2024/9/10 上午10:24, maobibo 写道:
>
>
> On 2024/9/9 下午9:13, gaosong wrote:
>> 在 2024/9/9 下午7:52, gaosong 写道:
>>>
>>>
>>> 在 2024/9/4 下午2:18, Bibo Mao 写道:
>>>> Six registers scr0 - scr3, eflags and ftop are added in percpu 
>>>> vmstate.
>>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are 
>>>> added
>>>> to save/restore lbt registers.
>>>>
>>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>>>> ---
>>>>   target/loongarch/cpu.h     | 12 ++++++++
>>>>   target/loongarch/kvm/kvm.c | 60 
>>>> ++++++++++++++++++++++++++++++++++++++
>>>>   target/loongarch/machine.c | 24 +++++++++++++++
>>>>   3 files changed, 96 insertions(+)
>>>>
>>>
>>> Reviewed-by: Song Gao <gaosong@loongson.cn>
>>>
>>> Thanks
>>> Song Gao
>> Hi,  this patch need rebase.
>>
>> Applying: target/loongarch: Implement lbt registers save/restore 
>> function
>> error: sha1 information is lacking or useless 
>> (target/loongarch/kvm/kvm.c).
>> error: could not build fake ancestor
>> Patch failed at 0001 target/loongarch: Implement lbt registers 
>> save/restore function
>
> Hi Song,
>
> It can apply with the latest qemu version on my side, only that it 
> fails to compile since kvm uapi header files need be updated.
>
> LBT patch on qemu side can be skipped here since it depends on LBT 
> patch merged on kernel side firstly.
>
Hi,

The LBT patches already merged on kernel side.
Could you update this series  and add a patch to support gdb LBT feature ?

Thanks.
Song Gao

> Regards
> Bibo Mao
>>
>>
>> Thanks.
>> Song Gao.
>>

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[maobibo]

Hi Tiezhu,

Does mainline gdb support to dump LBT register now?

Regards
Bibo Mao

On 2024/9/23 下午9:02, gaosong wrote:
> 在 2024/9/10 上午10:24, maobibo 写道:
>>
>>
>> On 2024/9/9 下午9:13, gaosong wrote:
>>> 在 2024/9/9 下午7:52, gaosong 写道:
>>>>
>>>>
>>>> 在 2024/9/4 下午2:18, Bibo Mao 写道:
>>>>> Six registers scr0 - scr3, eflags and ftop are added in percpu 
>>>>> vmstate.
>>>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are 
>>>>> added
>>>>> to save/restore lbt registers.
>>>>>
>>>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>>>>> ---
>>>>>   target/loongarch/cpu.h     | 12 ++++++++
>>>>>   target/loongarch/kvm/kvm.c | 60 
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>>   target/loongarch/machine.c | 24 +++++++++++++++
>>>>>   3 files changed, 96 insertions(+)
>>>>>
>>>>
>>>> Reviewed-by: Song Gao <gaosong@loongson.cn>
>>>>
>>>> Thanks
>>>> Song Gao
>>> Hi,  this patch need rebase.
>>>
>>> Applying: target/loongarch: Implement lbt registers save/restore 
>>> function
>>> error: sha1 information is lacking or useless 
>>> (target/loongarch/kvm/kvm.c).
>>> error: could not build fake ancestor
>>> Patch failed at 0001 target/loongarch: Implement lbt registers 
>>> save/restore function
>>
>> Hi Song,
>>
>> It can apply with the latest qemu version on my side, only that it 
>> fails to compile since kvm uapi header files need be updated.
>>
>> LBT patch on qemu side can be skipped here since it depends on LBT 
>> patch merged on kernel side firstly.
>>
> Hi,
> 
> The LBT patches already merged on kernel side.
> Could you update this series  and add a patch to support gdb LBT feature ?
> 
> Thanks.
> Song Gao
> 
>> Regards
>> Bibo Mao
>>>
>>>
>>> Thanks.
>>> Song Gao.
>>>
> 

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[Tiezhu Yang]

On 09/24/2024 09:28 AM, maobibo wrote:
> Hi Tiezhu,
>
> Does mainline gdb support to dump LBT register now?

Yes, here are the related gdb commit and kernel code:

https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=e4d74c01e773

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h#n59

Thanks,
Tiezhu

Re: [PATCH v4 2/2] target/loongarch: Implement lbt registers save/restore function

[maobibo]

On 2024/9/23 下午9:02, gaosong wrote:
> 在 2024/9/10 上午10:24, maobibo 写道:
>>
>>
>> On 2024/9/9 下午9:13, gaosong wrote:
>>> 在 2024/9/9 下午7:52, gaosong 写道:
>>>>
>>>>
>>>> 在 2024/9/4 下午2:18, Bibo Mao 写道:
>>>>> Six registers scr0 - scr3, eflags and ftop are added in percpu 
>>>>> vmstate.
>>>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are 
>>>>> added
>>>>> to save/restore lbt registers.
>>>>>
>>>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>>>>> ---
>>>>>   target/loongarch/cpu.h     | 12 ++++++++
>>>>>   target/loongarch/kvm/kvm.c | 60 
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>>   target/loongarch/machine.c | 24 +++++++++++++++
>>>>>   3 files changed, 96 insertions(+)
>>>>>
>>>>
>>>> Reviewed-by: Song Gao <gaosong@loongson.cn>
>>>>
>>>> Thanks
>>>> Song Gao
>>> Hi,  this patch need rebase.
>>>
>>> Applying: target/loongarch: Implement lbt registers save/restore 
>>> function
>>> error: sha1 information is lacking or useless 
>>> (target/loongarch/kvm/kvm.c).
>>> error: could not build fake ancestor
>>> Patch failed at 0001 target/loongarch: Implement lbt registers 
>>> save/restore function
>>
>> Hi Song,
>>
>> It can apply with the latest qemu version on my side, only that it 
>> fails to compile since kvm uapi header files need be updated.
>>
>> LBT patch on qemu side can be skipped here since it depends on LBT 
>> patch merged on kernel side firstly.
>>
> Hi,
> 
> The LBT patches already merged on kernel side.
> Could you update this series  and add a patch to support gdb LBT feature ?
Hi Song,

QEMU TCG does not support LBT, and kernel does not use LBT and it is 
only saved and restored in kernel mode. gdb can be used to debug user 
app if there is such requirements.

There is no obvious requirement to debug kernel with LBT function, how 
about adding the function if there is such requirement in future.

Regards
Bibo Mao
> 
> Thanks.
> Song Gao
> 
>> Regards
>> Bibo Mao
>>>
>>>
>>> Thanks.
>>> Song Gao.
>>>