* [PATCH v2] target/riscv/cpu_helper: Fix linking problem with semihosting disabled
@ 2024-09-06 9:48 Thomas Huth
2024-09-09 3:51 ` Alistair Francis
2024-09-10 4:56 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Thomas Huth @ 2024-09-06 9:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng
Cc: Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Peter Maydell,
Philippe Mathieu-Daudé
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
reference to `do_common_semihosting'
We always want semihosting to be enabled if TCG is available, so change
the "imply" statements in the Kconfig file to "select", and make sure to
avoid calling into do_common_semihosting() if TCG is not available.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
v2: Use "select" in the Kconfig file, and "CONFIG_TCG" in the #ifdef
target/riscv/cpu_helper.c | 2 ++
target/riscv/Kconfig | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 395a1d9140..dc147181a3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1674,10 +1674,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (!async) {
/* set tval to badaddr for traps with address information */
switch (cause) {
+#ifdef CONFIG_TCG
case RISCV_EXCP_SEMIHOST:
do_common_semihosting(cs);
env->pc += 4;
return;
+#endif
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS:
diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
index c332616d36..11bc09b414 100644
--- a/target/riscv/Kconfig
+++ b/target/riscv/Kconfig
@@ -1,9 +1,9 @@
config RISCV32
bool
- imply ARM_COMPATIBLE_SEMIHOSTING if TCG
+ select ARM_COMPATIBLE_SEMIHOSTING if TCG
select DEVICE_TREE # needed by boot.c
config RISCV64
bool
- imply ARM_COMPATIBLE_SEMIHOSTING if TCG
+ select ARM_COMPATIBLE_SEMIHOSTING if TCG
select DEVICE_TREE # needed by boot.c
--
2.46.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] target/riscv/cpu_helper: Fix linking problem with semihosting disabled
2024-09-06 9:48 [PATCH v2] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Thomas Huth
@ 2024-09-09 3:51 ` Alistair Francis
2024-09-10 4:56 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2024-09-09 3:51 UTC (permalink / raw)
To: Thomas Huth
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Peter Maydell, Philippe Mathieu-Daudé
On Fri, Sep 6, 2024 at 7:50 PM Thomas Huth <thuth@redhat.com> wrote:
>
> If QEMU has been configured with "--without-default-devices", the build
> is currently failing with:
>
> /usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
> in function `riscv_cpu_do_interrupt':
> .../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
> reference to `do_common_semihosting'
>
> We always want semihosting to be enabled if TCG is available, so change
> the "imply" statements in the Kconfig file to "select", and make sure to
> avoid calling into do_common_semihosting() if TCG is not available.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> v2: Use "select" in the Kconfig file, and "CONFIG_TCG" in the #ifdef
>
> target/riscv/cpu_helper.c | 2 ++
> target/riscv/Kconfig | 4 ++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 395a1d9140..dc147181a3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1674,10 +1674,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> if (!async) {
> /* set tval to badaddr for traps with address information */
> switch (cause) {
> +#ifdef CONFIG_TCG
> case RISCV_EXCP_SEMIHOST:
> do_common_semihosting(cs);
> env->pc += 4;
> return;
> +#endif
> case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
> case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
> case RISCV_EXCP_LOAD_ADDR_MIS:
> diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
> index c332616d36..11bc09b414 100644
> --- a/target/riscv/Kconfig
> +++ b/target/riscv/Kconfig
> @@ -1,9 +1,9 @@
> config RISCV32
> bool
> - imply ARM_COMPATIBLE_SEMIHOSTING if TCG
> + select ARM_COMPATIBLE_SEMIHOSTING if TCG
> select DEVICE_TREE # needed by boot.c
>
> config RISCV64
> bool
> - imply ARM_COMPATIBLE_SEMIHOSTING if TCG
> + select ARM_COMPATIBLE_SEMIHOSTING if TCG
> select DEVICE_TREE # needed by boot.c
> --
> 2.46.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] target/riscv/cpu_helper: Fix linking problem with semihosting disabled
2024-09-06 9:48 [PATCH v2] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Thomas Huth
2024-09-09 3:51 ` Alistair Francis
@ 2024-09-10 4:56 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2024-09-10 4:56 UTC (permalink / raw)
To: Thomas Huth
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Peter Maydell, Philippe Mathieu-Daudé
On Fri, Sep 6, 2024 at 7:50 PM Thomas Huth <thuth@redhat.com> wrote:
>
> If QEMU has been configured with "--without-default-devices", the build
> is currently failing with:
>
> /usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
> in function `riscv_cpu_do_interrupt':
> .../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
> reference to `do_common_semihosting'
>
> We always want semihosting to be enabled if TCG is available, so change
> the "imply" statements in the Kconfig file to "select", and make sure to
> avoid calling into do_common_semihosting() if TCG is not available.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v2: Use "select" in the Kconfig file, and "CONFIG_TCG" in the #ifdef
>
> target/riscv/cpu_helper.c | 2 ++
> target/riscv/Kconfig | 4 ++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 395a1d9140..dc147181a3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1674,10 +1674,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> if (!async) {
> /* set tval to badaddr for traps with address information */
> switch (cause) {
> +#ifdef CONFIG_TCG
> case RISCV_EXCP_SEMIHOST:
> do_common_semihosting(cs);
> env->pc += 4;
> return;
> +#endif
> case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
> case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
> case RISCV_EXCP_LOAD_ADDR_MIS:
> diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
> index c332616d36..11bc09b414 100644
> --- a/target/riscv/Kconfig
> +++ b/target/riscv/Kconfig
> @@ -1,9 +1,9 @@
> config RISCV32
> bool
> - imply ARM_COMPATIBLE_SEMIHOSTING if TCG
> + select ARM_COMPATIBLE_SEMIHOSTING if TCG
> select DEVICE_TREE # needed by boot.c
>
> config RISCV64
> bool
> - imply ARM_COMPATIBLE_SEMIHOSTING if TCG
> + select ARM_COMPATIBLE_SEMIHOSTING if TCG
> select DEVICE_TREE # needed by boot.c
> --
> 2.46.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-09-10 4:56 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-06 9:48 [PATCH v2] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Thomas Huth
2024-09-09 3:51 ` Alistair Francis
2024-09-10 4:56 ` Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).