From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@kaod.org, fbarrat@linux.ibm.com,
npiggin@gmail.com, milesg@linux.ibm.com
Subject: [PATCH v2 14/14] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths
Date: Mon, 9 Sep 2024 16:10:38 -0500 [thread overview]
Message-ID: <20240909211038.27440-15-kowal@linux.ibm.com> (raw)
In-Reply-To: <20240909211038.27440-1-kowal@linux.ibm.com>
Some of the TIMA Special CI operations perform the same operation at
alternative byte offsets and lengths. The following
xive2_tm_opertions[] table entries are missing when they exist for
other offsets/sizes and have been added:
- lwz@0x810 Pull/Invalidate O/S Context to register added
lwz@0x818 exists
ld @0x818 exists
- lwz@0x820 Pull Pool Context to register added
lwz@0x828 exists
ld @0x828 exists
- lwz@0x830 Pull Thread Context to register added
lbz@0x838 exists
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive_regs.h | 7 ++++++-
hw/intc/xive.c | 6 ++++++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 5b11463777..326327fc79 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -124,12 +124,17 @@
#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */
/* context */
#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
+#define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */
+ /* context to reg */
#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */
/* context to reg */
+#define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */
+ /* context to reg */
#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */
/* context to reg */
#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
-#define TM_SPC_PULL_PHYS_CTX 0x838 /* Pull phys ctx to reg */
+#define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */
+#define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */
#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */
/* line */
#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3ce86b6895..efcb63e8aa 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -614,18 +614,24 @@ static const XiveTmOp xive2_tm_operations[] = {
xive_tm_ack_os_reg },
{ XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending,
NULL },
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL,
+ xive2_tm_pull_os_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL,
xive2_tm_pull_os_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL,
xive2_tm_pull_os_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL,
xive_tm_ack_hv_reg },
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL,
+ xive_tm_pull_pool_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL,
xive_tm_pull_pool_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL,
xive_tm_pull_pool_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol,
NULL },
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL,
+ xive_tm_pull_phys_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL,
xive_tm_pull_phys_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol,
--
2.43.0
prev parent reply other threads:[~2024-09-09 21:13 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 21:10 [PATCH v2 00/14] XIVE2 changes for TIMA operations Michael Kowal
2024-09-09 21:10 ` [PATCH v2 01/14] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Michael Kowal
2024-09-09 21:10 ` [PATCH v2 02/14] pnv/xive2: Define OGEN field in the TIMA Michael Kowal
2024-09-09 21:10 ` [PATCH v2 03/14] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Michael Kowal
2024-09-10 17:21 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation Michael Kowal
2024-09-09 21:10 ` [PATCH v2 05/14] ppc/xive2: Dump more NVP state with 'info pic' Michael Kowal
2024-09-10 17:23 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 06/14] ppc/xive2: Dump the VP-group and crowd tables " Michael Kowal
2024-09-10 17:25 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 07/14] ppc/xive2: Allow 1-byte write of Target field in TIMA Michael Kowal
2024-09-09 21:10 ` [PATCH v2 08/14] ppc/xive2: Support "Pull Thread Context to Register" operation Michael Kowal
2024-09-09 21:10 ` [PATCH v2 09/14] ppc/xive2: Change context/ring specific functions to be generic Michael Kowal
2024-09-12 6:27 ` Cédric Le Goater
2024-09-12 16:41 ` Mike Kowal
2024-09-09 21:10 ` [PATCH v2 10/14] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Michael Kowal
2024-09-12 6:24 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 11/14] pnv/xive: Add special handling for pool targets Michael Kowal
2024-09-10 17:32 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 12/14] pnv/xive: Update PIPR when updating CPPR Michael Kowal
2024-09-10 17:30 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 13/14] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Michael Kowal
2024-09-09 21:10 ` Michael Kowal [this message]
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