From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@kaod.org, fbarrat@linux.ibm.com,
npiggin@gmail.com, milesg@linux.ibm.com
Subject: [PATCH v2 05/14] ppc/xive2: Dump more NVP state with 'info pic'
Date: Mon, 9 Sep 2024 16:10:29 -0500 [thread overview]
Message-ID: <20240909211038.27440-6-kowal@linux.ibm.com> (raw)
In-Reply-To: <20240909211038.27440-1-kowal@linux.ibm.com>
From: Frederic Barrat <fbarrat@linux.ibm.com>
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP
belongs to a VP group.
Also, print the Reporting Cache Line address, if defined.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive2_regs.h | 1 +
hw/intc/xive2.c | 10 ++++++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 7acf7dccf3..d71a54f9ff 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -151,6 +151,7 @@ typedef struct Xive2Nvp {
#define NVP2_W0_VALID PPC_BIT32(0)
#define NVP2_W0_HW PPC_BIT32(7)
#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
+#define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31)
uint32_t w1;
#define NVP2_W1_CO PPC_BIT32(13)
#define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index fbd05aa9f5..ac581fa195 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -161,14 +161,20 @@ void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf)
{
uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
+ uint64_t cache_line = xive2_nvp_reporting_addr(nvp);
if (!xive2_nvp_is_valid(nvp)) {
return;
}
- g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x",
+ g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x",
nvp_idx, eq_blk, eq_idx,
- xive_get_field32(NVP2_W2_IPB, nvp->w2));
+ xive_get_field32(NVP2_W2_IPB, nvp->w2),
+ xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0));
+ if (cache_line) {
+ g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line);
+ }
+
/*
* When the NVP is HW controlled, more fields are updated
*/
--
2.43.0
next prev parent reply other threads:[~2024-09-09 21:11 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 21:10 [PATCH v2 00/14] XIVE2 changes for TIMA operations Michael Kowal
2024-09-09 21:10 ` [PATCH v2 01/14] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Michael Kowal
2024-09-09 21:10 ` [PATCH v2 02/14] pnv/xive2: Define OGEN field in the TIMA Michael Kowal
2024-09-09 21:10 ` [PATCH v2 03/14] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Michael Kowal
2024-09-10 17:21 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation Michael Kowal
2024-09-09 21:10 ` Michael Kowal [this message]
2024-09-10 17:23 ` [PATCH v2 05/14] ppc/xive2: Dump more NVP state with 'info pic' Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 06/14] ppc/xive2: Dump the VP-group and crowd tables " Michael Kowal
2024-09-10 17:25 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 07/14] ppc/xive2: Allow 1-byte write of Target field in TIMA Michael Kowal
2024-09-09 21:10 ` [PATCH v2 08/14] ppc/xive2: Support "Pull Thread Context to Register" operation Michael Kowal
2024-09-09 21:10 ` [PATCH v2 09/14] ppc/xive2: Change context/ring specific functions to be generic Michael Kowal
2024-09-12 6:27 ` Cédric Le Goater
2024-09-12 16:41 ` Mike Kowal
2024-09-09 21:10 ` [PATCH v2 10/14] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Michael Kowal
2024-09-12 6:24 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 11/14] pnv/xive: Add special handling for pool targets Michael Kowal
2024-09-10 17:32 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 12/14] pnv/xive: Update PIPR when updating CPPR Michael Kowal
2024-09-10 17:30 ` Cédric Le Goater
2024-09-09 21:10 ` [PATCH v2 13/14] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Michael Kowal
2024-09-09 21:10 ` [PATCH v2 14/14] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths Michael Kowal
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