From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com,
Deepak Gupta <debug@rivosinc.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v14 17/20] target/riscv: compressed encodings for sspush and sspopchk
Date: Thu, 12 Sep 2024 16:53:17 -0700 [thread overview]
Message-ID: <20240912235320.3768582-18-debug@rivosinc.com> (raw)
In-Reply-To: <20240912235320.3768582-1-debug@rivosinc.com>
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 3953bcf82d..bf893d1c2e 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -140,6 +140,10 @@ sw 110 ... ... .. ... 00 @cs_w
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
{
+ # c.sspush x1 carving out of zcmops
+ sspush 011 0 00001 00000 01 &r2_s rs2=1 rs1=0
+ # c.sspopchk x5 carving out of zcmops
+ sspopchk 011 0 00101 00000 01 &r2 rs1=5 rd=0
c_mop_n 011 0 0 n:3 1 00000 01
illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
addi 011 . 00010 ..... 01 @c_addi16sp
--
2.45.0
next prev parent reply other threads:[~2024-09-12 23:58 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 23:53 [PATCH v14 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-09-12 23:53 ` Deepak Gupta [this message]
2024-09-12 23:53 ` [PATCH v14 18/20] disas/riscv: enable disassembly for " Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 20/20] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
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