From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com,
Deepak Gupta <debug@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v14 18/20] disas/riscv: enable disassembly for zicfiss instructions
Date: Thu, 12 Sep 2024 16:53:18 -0700 [thread overview]
Message-ID: <20240912235320.3768582-19-debug@rivosinc.com> (raw)
In-Reply-To: <20240912235320.3768582-1-debug@rivosinc.com>
Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap.
Disasembly is only enabled if zimop and zicfiss ext is set to true.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 40 +++++++++++++++++++++++++++++++++++++++-
disas/riscv.h | 1 +
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2942a5800f..0f9ecd8a14 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -977,6 +977,11 @@ typedef enum {
rv_op_wrs_sto = 946,
rv_op_wrs_nto = 947,
rv_op_lpad = 948,
+ rv_op_sspush = 949,
+ rv_op_sspopchk = 950,
+ rv_op_ssrdp = 951,
+ rv_op_ssamoswap_w = 952,
+ rv_op_ssamoswap_d = 953,
} rv_op;
/* register names */
@@ -2238,6 +2243,11 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
+ { "sspush", rv_codec_r, rv_fmt_rs2, NULL, 0, 0, 0 },
+ { "sspopchk", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
+ { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
+ { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2255,6 +2265,7 @@ static const char *csr_name(int csrno)
case 0x0009: return "vxsat";
case 0x000a: return "vxrm";
case 0x000f: return "vcsr";
+ case 0x0011: return "ssp";
case 0x0015: return "seed";
case 0x0017: return "jvt";
case 0x0040: return "uscratch";
@@ -3081,6 +3092,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 66: op = rv_op_amoor_w; break;
case 67: op = rv_op_amoor_d; break;
case 68: op = rv_op_amoor_q; break;
+ case 74: op = rv_op_ssamoswap_w; break;
+ case 75: op = rv_op_ssamoswap_d; break;
case 96: op = rv_op_amoand_b; break;
case 97: op = rv_op_amoand_h; break;
case 98: op = rv_op_amoand_w; break;
@@ -4034,7 +4047,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_csrrc; break;
case 4:
if (dec->cfg->ext_zimop) {
- int imm_mop5, imm_mop3;
+ int imm_mop5, imm_mop3, reg_num;
if ((extract32(inst, 22, 10) & 0b1011001111)
== 0b1000000111) {
imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
@@ -4042,11 +4055,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
extract32(inst, 26, 2)),
4, 1, extract32(inst, 30, 1));
op = rv_mop_r_0 + imm_mop5;
+ /* if zicfiss enabled and mop5 is shadow stack */
+ if (dec->cfg->ext_zicfiss &&
+ ((imm_mop5 & 0b11100) == 0b11100)) {
+ /* rs1=0 means ssrdp */
+ if ((inst & (0b011111 << 15)) == 0) {
+ op = rv_op_ssrdp;
+ }
+ /* rd=0 means sspopchk */
+ reg_num = (inst >> 15) & 0b011111;
+ if (((inst & (0b011111 << 7)) == 0) &&
+ ((reg_num == 1) || (reg_num == 5))) {
+ op = rv_op_sspopchk;
+ }
+ }
} else if ((extract32(inst, 25, 7) & 0b1011001)
== 0b1000001) {
imm_mop3 = deposit32(extract32(inst, 26, 2),
2, 1, extract32(inst, 30, 1));
op = rv_mop_rr_0 + imm_mop3;
+ /* if zicfiss enabled and mop3 is shadow stack */
+ if (dec->cfg->ext_zicfiss &&
+ ((imm_mop3 & 0b111) == 0b111)) {
+ /* rs1=0 and rd=0 means sspush */
+ reg_num = (inst >> 20) & 0b011111;
+ if (((inst & (0b011111 << 15)) == 0) &&
+ ((inst & (0b011111 << 7)) == 0) &&
+ ((reg_num == 1) || (reg_num == 5))) {
+ op = rv_op_sspush;
+ }
+ }
}
}
break;
diff --git a/disas/riscv.h b/disas/riscv.h
index 1182457aff..4895c5a301 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -224,6 +224,7 @@ enum {
#define rv_fmt_none "O\t"
#define rv_fmt_rs1 "O\t1"
+#define rv_fmt_rs2 "O\t2"
#define rv_fmt_offset "O\to"
#define rv_fmt_pred_succ "O\tp,s"
#define rv_fmt_rs1_rs2 "O\t1,2"
--
2.45.0
next prev parent reply other threads:[~2024-09-12 23:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 23:53 [PATCH v14 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 17/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-09-12 23:53 ` Deepak Gupta [this message]
2024-09-12 23:53 ` [PATCH v14 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-09-12 23:53 ` [PATCH v14 20/20] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
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