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From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Mark Corbin <mark@dibsco.co.uk>,
	qemu-riscv@nongnu.org, Warner Losh <imp@bsdimp.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Ajeet Singh <itachis@FreeBSD.org>,
	Jessica Clarke <jrtc27@jrtc27.com>,
	Kyle Evans <kevans@FreeBSD.org>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v7 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling
Date: Tue, 17 Sep 2024 01:51:04 +1000	[thread overview]
Message-ID: <20240916155119.14610-3-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org>

From: Mark Corbin <mark@dibsco.co.uk>

Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.

Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index f8d85e01ad..9c31d9dc4c 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -37,4 +37,98 @@ static inline void target_cpu_init(CPURISCVState *env,
     env->pc = regs->sepc;
 }
 
+static inline void target_cpu_loop(CPURISCVState *env)
+{
+    CPUState *cs = env_cpu(env);
+    int trapnr;
+    abi_long ret;
+    unsigned int syscall_num;
+    int32_t signo, code;
+
+    for (;;) {
+        cpu_exec_start(cs);
+        trapnr = cpu_exec(cs);
+        cpu_exec_end(cs);
+        process_queued_cpu_work(cs);
+
+        signo = 0;
+
+        switch (trapnr) {
+        case EXCP_INTERRUPT:
+            /* just indicate that signals should be handled asap */
+            break;
+        case EXCP_ATOMIC:
+            cpu_exec_step_atomic(cs);
+            break;
+        case RISCV_EXCP_U_ECALL:
+            syscall_num = env->gpr[xT0];
+            env->pc += TARGET_INSN_SIZE;
+            /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */
+            if (TARGET_FREEBSD_NR___syscall == syscall_num ||
+                TARGET_FREEBSD_NR_syscall == syscall_num) {
+                ret = do_freebsd_syscall(env,
+                                         env->gpr[xA0],
+                                         env->gpr[xA1],
+                                         env->gpr[xA2],
+                                         env->gpr[xA3],
+                                         env->gpr[xA4],
+                                         env->gpr[xA5],
+                                         env->gpr[xA6],
+                                         env->gpr[xA7],
+                                         0);
+            } else {
+                ret = do_freebsd_syscall(env,
+                                         syscall_num,
+                                         env->gpr[xA0],
+                                         env->gpr[xA1],
+                                         env->gpr[xA2],
+                                         env->gpr[xA3],
+                                         env->gpr[xA4],
+                                         env->gpr[xA5],
+                                         env->gpr[xA6],
+                                         env->gpr[xA7]
+                    );
+            }
+
+            /*
+             * Compare to cpu_set_syscall_retval() in
+             * riscv/riscv/vm_machdep.c
+             */
+            if (ret >= 0) {
+                env->gpr[xA0] = ret;
+                env->gpr[xT0] = 0;
+            } else if (ret == -TARGET_ERESTART) {
+                env->pc -= TARGET_INSN_SIZE;
+            } else if (ret != -TARGET_EJUSTRETURN) {
+                env->gpr[xA0] = -ret;
+                env->gpr[xT0] = 1;
+            }
+            break;
+        case RISCV_EXCP_ILLEGAL_INST:
+            signo = TARGET_SIGILL;
+            code = TARGET_ILL_ILLOPC;
+            break;
+        case RISCV_EXCP_BREAKPOINT:
+            signo = TARGET_SIGTRAP;
+            code = TARGET_TRAP_BRKPT;
+            break;
+        case EXCP_DEBUG:
+            signo = TARGET_SIGTRAP;
+            code = TARGET_TRAP_BRKPT;
+            break;
+        default:
+            fprintf(stderr, "qemu: unhandled CPU exception "
+                "0x%x - aborting\n", trapnr);
+            cpu_dump_state(cs, stderr, 0);
+            abort();
+        }
+
+        if (signo) {
+            force_sig_fault(signo, code, env->pc);
+        }
+
+        process_pending_signals(env);
+    }
+}
+
 #endif /* TARGET_ARCH_CPU_H */
-- 
2.34.1



  parent reply	other threads:[~2024-09-16 15:52 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-16 15:51 [PATCH v7 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-09-16 15:51 ` Ajeet Singh [this message]
2024-09-16 15:51 ` [PATCH v7 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-09-16 17:58 ` [PATCH v7 00/17] bsd-user: Comprehensive RISCV Support Daniel Henrique Barboza
2024-09-24  1:42 ` Alistair Francis

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