From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Mark Corbin <mark@dibsco.co.uk>,
qemu-riscv@nongnu.org, Warner Losh <imp@bsdimp.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Ajeet Singh <itachis@FreeBSD.org>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v7 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions
Date: Tue, 17 Sep 2024 01:51:05 +1000 [thread overview]
Message-ID: <20240916155119.14610-4-itachis@FreeBSD.org> (raw)
In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org>
From: Mark Corbin <mark@dibsco.co.uk>
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index 9c31d9dc4c..a93ea3915a 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -131,4 +131,18 @@ static inline void target_cpu_loop(CPURISCVState *env)
}
}
+static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->gpr[xSP] = newsp;
+ }
+
+ env->gpr[xA0] = 0;
+ env->gpr[xT0] = 0;
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
#endif /* TARGET_ARCH_CPU_H */
--
2.34.1
next prev parent reply other threads:[~2024-09-16 15:52 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-16 15:51 [PATCH v7 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-09-16 15:51 ` Ajeet Singh [this message]
2024-09-16 15:51 ` [PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-09-16 15:51 ` [PATCH v7 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-09-16 17:58 ` [PATCH v7 00/17] bsd-user: Comprehensive RISCV Support Daniel Henrique Barboza
2024-09-24 1:42 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240916155119.14610-4-itachis@FreeBSD.org \
--to=itachis6234@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=dbarboza@ventanamicro.com \
--cc=imp@bsdimp.com \
--cc=itachis@FreeBSD.org \
--cc=mark@dibsco.co.uk \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).