From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 02/12] hw/i2c/aspeed: Support discontinuous register memory region of I2C bus
Date: Mon, 16 Sep 2024 20:56:58 +0200 [thread overview]
Message-ID: <20240916185708.574546-3-clg@redhat.com> (raw)
In-Reply-To: <20240916185708.574546-1-clg@redhat.com>
From: Jamin Lin <jamin_lin@aspeedtech.com>
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0x37F: Device 2
0x400 - 0x47F: Device 3
0x500 - 0x57F: Device 4
0x600 - 0x67F: Device 5
0x700 - 0x77F: Device 6
0x800 - 0x87F: Device 7
0x900 - 0x97F: Device 8
0xA00 - 0xA7F: Device 9
0xB00 - 0xB7F: Device 10
0xC00 - 0xC7F: Device 11
0xD00 - 0xD7F: Device 12
0xE00 - 0xE7F: Device 13
0xF00 – 0xF7F: Device 14
0x1000 – 0x107F: Device 15
Introduce a new class attribute to make user set each I2C bus gap size.
Update formula to create all I2C bus register memory regions.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/i2c/aspeed_i2c.h | 1 +
hw/i2c/aspeed_i2c.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index fad5e9259a51..02ede859067e 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -275,6 +275,7 @@ struct AspeedI2CClass {
uint8_t num_busses;
uint8_t reg_size;
+ uint32_t reg_gap_size;
uint8_t gap;
qemu_irq (*bus_get_irq)(AspeedI2CBus *);
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index f19891371426..ee30243c25f9 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1012,6 +1012,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedI2CState *s = ASPEED_I2C(dev);
AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
+ uint32_t reg_offset = aic->reg_size + aic->reg_gap_size;
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
@@ -1034,7 +1035,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
return;
}
- memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset),
+ memory_region_add_subregion(&s->iomem, reg_offset * (i + offset),
&s->busses[i].mr);
}
--
2.46.0
next prev parent reply other threads:[~2024-09-16 19:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-16 18:56 [PULL 00/12] aspeed queue Cédric Le Goater
2024-09-16 18:56 ` [PULL 01/12] hw/gpio/aspeed_gpio: Avoid shift into sign bit Cédric Le Goater
2024-09-16 18:56 ` Cédric Le Goater [this message]
2024-09-16 18:56 ` [PULL 03/12] hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus Cédric Le Goater
2024-09-16 18:57 ` [PULL 04/12] hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus Cédric Le Goater
2024-09-16 18:57 ` [PULL 05/12] hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus Cédric Le Goater
2024-09-16 18:57 ` [PULL 06/12] hw/i2c/aspeed: Add AST2700 support Cédric Le Goater
2024-09-16 18:57 ` [PULL 07/12] hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses Cédric Le Goater
2024-09-16 18:57 ` [PULL 08/12] hw/i2c/aspeed: Add support for " Cédric Le Goater
2024-09-16 18:57 ` [PULL 09/12] aspeed/soc: Introduce a new API to get the device irq Cédric Le Goater
2024-09-16 18:57 ` [PULL 10/12] aspeed/soc: Support I2C for AST2700 Cédric Le Goater
2024-09-16 18:57 ` [PULL 11/12] aspeed: Add tmp105 in i2c bus 0 " Cédric Le Goater
2024-09-16 18:57 ` [PULL 12/12] machine_aspeed.py: Update to test I2C " Cédric Le Goater
2024-09-17 13:00 ` [PULL 00/12] aspeed queue Peter Maydell
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