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From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	richard.henderson@linaro.org, negge@google.com,
	Max Chou <max.chou@sifive.com>
Subject: [PATCH v6 2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us
Date: Thu, 19 Sep 2024 01:14:07 +0800	[thread overview]
Message-ID: <20240918171412.150107-3-max.chou@sifive.com> (raw)
In-Reply-To: <20240918171412.150107-1-max.chou@sifive.com>

Because the real vl (evl) of vext_ldst_us may be different (e.g.
vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function
should be replaced by checking evl in vext_ldst_us.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/vector_helper.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 87d2399c7e3..967bb2687ae 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -276,7 +276,10 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
     uint32_t max_elems = vext_max_elems(desc, log2_esz);
     uint32_t esz = 1 << log2_esz;
 
-    VSTART_CHECK_EARLY_EXIT(env);
+    if (env->vstart >= evl) {
+        env->vstart = 0;
+        return;
+    }
 
     /* load bytes from guest memory */
     for (i = env->vstart; i < evl; env->vstart = ++i) {
-- 
2.34.1



  parent reply	other threads:[~2024-09-18 17:16 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-18 17:14 [PATCH v6 0/7] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions Max Chou
2024-09-18 17:14 ` [PATCH v6 1/7] target/riscv: Set vdata.vm field for vector load/store whole register instructions Max Chou
2024-10-29 18:58   ` Daniel Henrique Barboza
2024-10-30 11:30     ` Richard Henderson
2024-09-18 17:14 ` Max Chou [this message]
2024-10-29 18:59   ` [PATCH v6 2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us Daniel Henrique Barboza
2024-09-18 17:14 ` [PATCH v6 3/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store Max Chou
2024-10-30 16:26   ` Daniel Henrique Barboza
2024-09-18 17:14 ` [PATCH v6 4/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store Max Chou
2024-10-30 16:31   ` Daniel Henrique Barboza
2024-09-18 17:14 ` [PATCH v6 5/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions Max Chou
2024-10-30 16:35   ` Daniel Henrique Barboza
2024-09-18 17:14 ` [PATCH v6 6/7] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions Max Chou
2024-10-29 19:07   ` Daniel Henrique Barboza
2024-09-18 17:14 ` [PATCH v6 7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Max Chou
2024-10-30 16:37   ` Daniel Henrique Barboza
2024-10-15  9:15 ` [PATCH v6 0/7] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions Max Chou
2024-11-05  3:37 ` Alistair Francis

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