From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Fabiano Rosas <farosas@suse.de>,
qemu-stable@nongnu.org, Claudio Fontana <cfontana@suse.de>,
Ilya Leoshkevich <iii@linux.ibm.com>
Subject: [PULL 22/31] target/ppc: Fix lxvx/stxvx facility check
Date: Sun, 22 Sep 2024 14:01:03 +0200 [thread overview]
Message-ID: <20240922120112.5067-23-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240922120112.5067-1-richard.henderson@linaro.org>
From: Fabiano Rosas <farosas@suse.de>
The XT check for the lxvx/stxvx instructions is currently
inverted. This was introduced during the move to decodetree.
>From the ISA:
Chapter 7. Vector-Scalar Extension Facility
Load VSX Vector Indexed X-form
lxvx XT,RA,RB
if TX=0 & MSR.VSX=0 then VSX_Unavailable()
if TX=1 & MSR.VEC=0 then Vector_Unavailable()
...
Let XT be the value 32×TX + T.
The code currently does the opposite:
if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
}
This was already fixed for lxv/stxv at commit "2cc0e449d1 (target/ppc:
Fix lxv/stxv MSR facility check)", but the indexed forms were missed.
Cc: qemu-stable@nongnu.org
Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from legacy to decodtree")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-ID: <20240911141651.6914-1-farosas@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vsx-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 40a87ddc4a..a869f30e86 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2244,7 +2244,7 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
- if (paired || a->rt >= 32) {
+ if (paired || a->rt < 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
--
2.43.0
next prev parent reply other threads:[~2024-09-22 12:08 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-22 12:00 [PULL 00/31] tcg + linux-user patch queue Richard Henderson
2024-09-22 12:00 ` [PULL 01/31] tcg: Return TCGOp from tcg_gen_op[1-6] Richard Henderson
2024-09-22 12:00 ` [PULL 02/31] tcg: Propagate new TCGOp to add_as_label_use Richard Henderson
2024-09-22 12:00 ` [PULL 03/31] tcg: Fix iteration step in 32-bit gvec operation Richard Henderson
2024-09-22 12:00 ` [PULL 04/31] tcg: Export vec_gen_6 Richard Henderson
2024-09-22 12:00 ` [PULL 05/31] tcg/i386: Split out tcg_out_vex_modrm_type Richard Henderson
2024-09-22 12:00 ` [PULL 06/31] tcg/i386: Do not expand cmp_vec early Richard Henderson
2024-09-22 12:00 ` [PULL 07/31] tcg/i386: Do not expand cmpsel_vec early Richard Henderson
2024-09-22 12:00 ` [PULL 08/31] tcg/ppc: Do not expand cmp_vec early Richard Henderson
2024-09-22 12:00 ` [PULL 09/31] tcg/s390x: " Richard Henderson
2024-09-22 12:00 ` [PULL 10/31] tcg/optimize: Fold movcond with true and false values identical Richard Henderson
2024-09-22 12:00 ` [PULL 11/31] tcg/optimize: Optimize cmp_vec and cmpsel_vec Richard Henderson
2024-09-22 12:00 ` [PULL 12/31] tcg/optimize: Optimize bitsel_vec Richard Henderson
2024-09-22 12:00 ` [PULL 13/31] tcg/i386: Optimize cmpsel with constant 0 operand 3 Richard Henderson
2024-09-22 12:00 ` [PULL 14/31] tcg/i386: Implement cmp_vec with avx512 insns Richard Henderson
2024-09-22 12:00 ` [PULL 15/31] tcg/i386: Add predicate parameters to tcg_out_evex_opc Richard Henderson
2024-09-22 12:00 ` [PULL 16/31] tcg/i386: Implement cmpsel_vec with avx512 insns Richard Henderson
2024-09-22 12:00 ` [PULL 17/31] tcg/i386: Implement vector TST{EQ,NE} for avx512 Richard Henderson
2024-09-22 12:00 ` [PULL 18/31] tcg/ppc: Implement cmpsel_vec Richard Henderson
2024-09-22 12:01 ` [PULL 19/31] tcg/ppc: Optimize cmpsel with constant 0/-1 arguments Richard Henderson
2024-09-22 12:01 ` [PULL 20/31] tcg/s390x: Implement cmpsel_vec Richard Henderson
2024-09-22 12:01 ` [PULL 21/31] tcg/s390x: Optimize cmpsel with constant 0/-1 arguments Richard Henderson
2024-09-22 12:01 ` Richard Henderson [this message]
2024-09-22 12:01 ` [PULL 23/31] linux-user: update syscall_nr.h to Linux v6.10 Richard Henderson
2024-09-22 12:01 ` [PULL 24/31] linux-user, mips: update syscall-args-o32.c.inc " Richard Henderson
2024-09-22 12:01 ` [PULL 25/31] linux-user: update syscall.tbl " Richard Henderson
2024-09-22 12:01 ` [PULL 26/31] linux-user,aarch64: move to syscalltbl file Richard Henderson
2024-09-22 12:01 ` [PULL 27/31] linux-user,openrisc: " Richard Henderson
2024-09-22 12:01 ` [PULL 28/31] linux-user,riscv: " Richard Henderson
2024-09-22 12:01 ` [PULL 29/31] linux-user,hexagon: " Richard Henderson
2024-09-22 12:01 ` [PULL 30/31] linux-user,loongarch: " Richard Henderson
2024-09-22 12:01 ` [PULL 31/31] linux-user: update syscall.tbl to Linux v6.11 Richard Henderson
2024-09-27 15:18 ` [PULL 00/31] tcg + linux-user patch queue Peter Maydell
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