From: Sebastian Huber <sebastian.huber@embedded-brains.de>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 0/2] Fix secondary CPU reset for Xilinx Zynq 7000
Date: Mon, 23 Sep 2024 05:56:30 +0200 [thread overview]
Message-ID: <20240923035632.81304-1-sebastian.huber@embedded-brains.de> (raw)
I recently added the support for CPU1 to the xilinx-zynq-a9 machine
(hw/arm/xilinx_zynq.c). However, the reset behaviour doesn't match exactly with
the hardware. After a system reset (SRST), the CPU1 should execute a wfe
instruction and then load the start address from 0xfffffff0:
https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1
Sebastian Huber (2):
hw/arm/boot: Use hooks if PSCI is disabled
hw/arm/xilinx_zynq: Add CPU1 reset
hw/arm/boot.c | 30 +++++++++++++++++++-----------
hw/arm/xilinx_zynq.c | 25 +++++++++++++++++++++++++
2 files changed, 44 insertions(+), 11 deletions(-)
--
2.35.3
next reply other threads:[~2024-09-23 3:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-23 3:56 Sebastian Huber [this message]
2024-09-23 3:56 ` [PATCH 1/2] hw/arm/boot: Use hooks if PSCI is disabled Sebastian Huber
2024-09-30 15:16 ` Peter Maydell
2024-10-04 1:24 ` Sebastian Huber
2024-10-04 10:36 ` Peter Maydell
2024-09-23 3:56 ` [PATCH 2/2] hw/arm/xilinx_zynq: Add CPU1 reset Sebastian Huber
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