From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH 1/5] hw/gpio/aspeed: Fix coding style
Date: Mon, 23 Sep 2024 17:42:01 +0800 [thread overview]
Message-ID: <20240923094206.1455783-2-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240923094206.1455783-1-jamin_lin@aspeedtech.com>
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/gpio/aspeed_gpio.c | 3 ++-
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 71756664dd..901b576144 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -340,7 +340,8 @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx,
value &= ~pin_mask;
}
- aspeed_gpio_update(s, &s->sets[set_idx], value, ~s->sets[set_idx].direction);
+ aspeed_gpio_update(s, &s->sets[set_idx], value,
+ ~s->sets[set_idx].direction);
}
/*
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
index 90a12ae318..39febda9ea 100644
--- a/include/hw/gpio/aspeed_gpio.h
+++ b/include/hw/gpio/aspeed_gpio.h
@@ -88,7 +88,7 @@ struct AspeedGPIOState {
qemu_irq irq;
qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET];
-/* Parallel GPIO Registers */
+ /* Parallel GPIO Registers */
uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
struct GPIOSets {
uint32_t data_value; /* Reflects pin values */
--
2.34.1
next prev parent reply other threads:[~2024-09-23 9:43 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via
2024-09-23 9:42 ` Jamin Lin via [this message]
2024-09-23 9:42 ` [PATCH 2/5] hw/gpio/aspeed: Support to set the different memory size Jamin Lin via
2024-09-23 9:42 ` [PATCH 3/5] hw/gpio/aspeed: Support different memory region ops Jamin Lin via
2024-09-23 9:42 ` [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support Jamin Lin via
2024-09-24 1:11 ` Andrew Jeffery
2024-09-24 3:03 ` Jamin Lin
2024-09-24 6:48 ` Jamin Lin
2024-09-25 0:00 ` Andrew Jeffery
2024-09-25 2:54 ` Jamin Lin
2024-09-24 23:55 ` Andrew Jeffery
2024-09-25 2:55 ` Jamin Lin
2024-09-23 9:42 ` [PATCH 5/5] aspeed/soc: Support GPIO for AST2700 Jamin Lin via
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