From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>, "Thomas Huth" <thuth@redhat.com>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com,
yunlin.tang@aspeedtech.com, "Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH v6 1/8] hw/gpio/aspeed: Fix coding style
Date: Mon, 30 Sep 2024 16:52:32 +0800 [thread overview]
Message-ID: <20240930085239.3089901-2-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240930085239.3089901-1-jamin_lin@aspeedtech.com>
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 71756664dd..00fb72a509 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -340,7 +340,8 @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx,
value &= ~pin_mask;
}
- aspeed_gpio_update(s, &s->sets[set_idx], value, ~s->sets[set_idx].direction);
+ aspeed_gpio_update(s, &s->sets[set_idx], value,
+ ~s->sets[set_idx].direction);
}
/*
@@ -629,7 +630,6 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset,
uint64_t data, uint32_t size)
{
-
AspeedGPIOState *s = ASPEED_GPIO(opaque);
AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
const GPIOSetProperties *props;
@@ -963,7 +963,7 @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name,
aspeed_gpio_set_pin_level(s, set_idx, pin, level);
}
-/****************** Setup functions ******************/
+/* Setup functions */
static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
[0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
[1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
index 90a12ae318..39febda9ea 100644
--- a/include/hw/gpio/aspeed_gpio.h
+++ b/include/hw/gpio/aspeed_gpio.h
@@ -88,7 +88,7 @@ struct AspeedGPIOState {
qemu_irq irq;
qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET];
-/* Parallel GPIO Registers */
+ /* Parallel GPIO Registers */
uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
struct GPIOSets {
uint32_t data_value; /* Reflects pin values */
--
2.34.1
next prev parent reply other threads:[~2024-09-30 8:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-30 8:52 [PATCH v6 0/8] Support GPIO for AST2700 Jamin Lin via
2024-09-30 8:52 ` Jamin Lin via [this message]
2024-09-30 8:52 ` [PATCH v6 2/8] hw/gpio/aspeed: Support to set the different memory size Jamin Lin via
2024-09-30 8:52 ` [PATCH v6 3/8] hw/gpio/aspeed: Support different memory region ops Jamin Lin via
2024-09-30 8:52 ` [PATCH v6 4/8] hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode Jamin Lin via
2024-09-30 8:52 ` [PATCH v6 5/8] hw/gpio/aspeed: Add AST2700 support Jamin Lin via
2024-09-30 8:52 ` [PATCH v6 6/8] aspeed/soc: Correct GPIO irq 130 for AST2700 Jamin Lin via
2024-09-30 9:11 ` [SPAM] " Cédric Le Goater
2024-09-30 8:52 ` [PATCH v6 7/8] aspeed/soc: Support GPIO " Jamin Lin via
2024-09-30 9:11 ` [SPAM] " Cédric Le Goater
2024-09-30 8:52 ` [PATCH v6 8/8] hw/gpio/aspeed: Add test case " Jamin Lin via
2024-09-30 16:36 ` Thomas Huth
2024-09-30 16:48 ` Cédric Le Goater
2024-09-30 17:23 ` Thomas Huth
2024-10-01 1:15 ` Jamin Lin
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