* [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h'
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-10-03 22:52 ` Richard Henderson
2024-09-30 9:10 ` [PATCH 02/12] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
` (11 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as cpu_is_bigendian_env().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/internal.h | 6 ++++++
target/mips/tcg/ldst_helper.c | 15 +++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index a9a22ea00e..1ce2bbf62d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,6 +9,7 @@
#define MIPS_INTERNAL_H
#include "exec/memattrs.h"
+#include "exec/memop.h"
#ifdef CONFIG_TCG
#include "tcg/tcg-internal.h"
#endif
@@ -287,6 +288,11 @@ static inline int mips_vp_active(CPUMIPSState *env)
return 1;
}
+static inline bool cpu_is_bigendian_env(CPUMIPSState *env)
+{
+ return extract32(env->CP0_Config0, CP0C0_BE, 1);
+}
+
static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index 97056d00a2..3d5cd2fdfa 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -53,11 +53,6 @@ HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
#endif /* !CONFIG_USER_ONLY */
-static inline bool cpu_is_bigendian(CPUMIPSState *env)
-{
- return extract32(env->CP0_Config0, CP0C0_BE, 1);
-}
-
static inline target_ulong get_lmask(CPUMIPSState *env,
target_ulong value, unsigned bits)
{
@@ -65,7 +60,7 @@ static inline target_ulong get_lmask(CPUMIPSState *env,
value &= mask;
- if (!cpu_is_bigendian(env)) {
+ if (!cpu_is_bigendian_env(env)) {
value ^= mask;
}
@@ -76,7 +71,7 @@ void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 32);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = cpu_is_bigendian_env(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
@@ -100,7 +95,7 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 32);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = cpu_is_bigendian_env(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
@@ -130,7 +125,7 @@ void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 64);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = cpu_is_bigendian_env(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
@@ -174,7 +169,7 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 64);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = cpu_is_bigendian_env(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h'
2024-09-30 9:10 ` [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h' Philippe Mathieu-Daudé
@ 2024-10-03 22:52 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-10-03 22:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
> In order to re-use cpu_is_bigendian(), declare it on "internal.h"
> after renaming it as cpu_is_bigendian_env().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/internal.h | 6 ++++++
> target/mips/tcg/ldst_helper.c | 15 +++++----------
> 2 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index a9a22ea00e..1ce2bbf62d 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -9,6 +9,7 @@
> #define MIPS_INTERNAL_H
>
> #include "exec/memattrs.h"
> +#include "exec/memop.h"
> #ifdef CONFIG_TCG
> #include "tcg/tcg-internal.h"
> #endif
> @@ -287,6 +288,11 @@ static inline int mips_vp_active(CPUMIPSState *env)
> return 1;
> }
>
> +static inline bool cpu_is_bigendian_env(CPUMIPSState *env)
> +{
> + return extract32(env->CP0_Config0, CP0C0_BE, 1);
> +}
Using the cpu_is_bigendian name for DisasContext is the error I think.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 02/12] target/mips: Introduce mo_endian_env() helper
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h' Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 03/12] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
` (10 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Introduce mo_endian_env() which returns the endian
MemOp corresponding to the vCPU env.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/internal.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1ce2bbf62d..5fe1af22ff 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -293,6 +293,11 @@ static inline bool cpu_is_bigendian_env(CPUMIPSState *env)
return extract32(env->CP0_Config0, CP0C0_BE, 1);
}
+static inline MemOp mo_endian_env(CPUMIPSState *env)
+{
+ return cpu_is_bigendian_env(env) ? MO_BE : MO_LE;
+}
+
static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 03/12] target/mips: Replace MO_TE by mo_endian_env() in get_pte()
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 01/12] target/mips: Declare cpu_is_bigendian_env() in 'internal.h' Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 02/12] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
` (9 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Replace compile-time MO_TE evaluation by runtime mo_endian_env()
one, which expand target endianness from vCPU env.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 3836137750..e98bb95951 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -601,7 +601,7 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op,
return false;
}
- oi = make_memop_idx(op | MO_TE, ptw_mmu_idx);
+ oi = make_memop_idx(op | mo_endian_env(env), ptw_mmu_idx);
if (op == MO_64) {
*pte = cpu_ldq_mmu(env, vaddr, oi, 0);
} else {
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 03/12] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-10-03 22:55 ` Richard Henderson
2024-09-30 9:10 ` [PATCH 05/12] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
` (8 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Functions are easier to rework than macros. Besides,
there is no gain here in inlining these.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/mips16e_translate.c.inc | 101 +++++++++++++-----------
1 file changed, 53 insertions(+), 48 deletions(-)
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 5cffe0e412..31bc14f9ca 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -122,11 +122,23 @@ enum {
static int xlat(int r)
{
- static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
+ static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
return map[r];
}
+static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_movi_tl(t2, -4);
+ gen_op_addr_add(ctx, t0, t0, t2);
+ gen_load_gpr(t1, regidx);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
+}
+
static void gen_mips16_save(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
@@ -196,46 +208,38 @@ static void gen_mips16_save(DisasContext *ctx,
gen_load_gpr(t0, 29);
-#define DECR_AND_STORE(reg) do { \
- tcg_gen_movi_tl(t2, -4); \
- gen_op_addr_add(ctx, t0, t0, t2); \
- gen_load_gpr(t1, reg); \
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \
- ctx->default_tcg_memop_mask); \
- } while (0)
-
if (do_ra) {
- DECR_AND_STORE(31);
+ decr_and_store(ctx, 31, t0);
}
switch (xsregs) {
case 7:
- DECR_AND_STORE(30);
+ decr_and_store(ctx, 30, t0);
/* Fall through */
case 6:
- DECR_AND_STORE(23);
+ decr_and_store(ctx, 23, t0);
/* Fall through */
case 5:
- DECR_AND_STORE(22);
+ decr_and_store(ctx, 22, t0);
/* Fall through */
case 4:
- DECR_AND_STORE(21);
+ decr_and_store(ctx, 21, t0);
/* Fall through */
case 3:
- DECR_AND_STORE(20);
+ decr_and_store(ctx, 20, t0);
/* Fall through */
case 2:
- DECR_AND_STORE(19);
+ decr_and_store(ctx, 19, t0);
/* Fall through */
case 1:
- DECR_AND_STORE(18);
+ decr_and_store(ctx, 18, t0);
}
if (do_s1) {
- DECR_AND_STORE(17);
+ decr_and_store(ctx, 17, t0);
}
if (do_s0) {
- DECR_AND_STORE(16);
+ decr_and_store(ctx, 16, t0);
}
switch (aregs) {
@@ -270,23 +274,34 @@ static void gen_mips16_save(DisasContext *ctx,
}
if (astatic > 0) {
- DECR_AND_STORE(7);
+ decr_and_store(ctx, 7, t0);
if (astatic > 1) {
- DECR_AND_STORE(6);
+ decr_and_store(ctx, 6, t0);
if (astatic > 2) {
- DECR_AND_STORE(5);
+ decr_and_store(ctx, 5, t0);
if (astatic > 3) {
- DECR_AND_STORE(4);
+ decr_and_store(ctx, 4, t0);
}
}
}
}
-#undef DECR_AND_STORE
tcg_gen_movi_tl(t2, -framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
}
+static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_movi_tl(t2, -4);
+ gen_op_addr_add(ctx, t0, t0, t2);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t1, regidx);
+}
+
static void gen_mips16_restore(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
@@ -294,52 +309,43 @@ static void gen_mips16_restore(DisasContext *ctx,
{
int astatic;
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
-#define DECR_AND_LOAD(reg) do { \
- tcg_gen_movi_tl(t2, -4); \
- gen_op_addr_add(ctx, t0, t0, t2); \
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \
- ctx->default_tcg_memop_mask); \
- gen_store_gpr(t1, reg); \
- } while (0)
-
if (do_ra) {
- DECR_AND_LOAD(31);
+ decr_and_load(ctx, 31, t0);
}
switch (xsregs) {
case 7:
- DECR_AND_LOAD(30);
+ decr_and_load(ctx, 30, t0);
/* Fall through */
case 6:
- DECR_AND_LOAD(23);
+ decr_and_load(ctx, 23, t0);
/* Fall through */
case 5:
- DECR_AND_LOAD(22);
+ decr_and_load(ctx, 22, t0);
/* Fall through */
case 4:
- DECR_AND_LOAD(21);
+ decr_and_load(ctx, 21, t0);
/* Fall through */
case 3:
- DECR_AND_LOAD(20);
+ decr_and_load(ctx, 20, t0);
/* Fall through */
case 2:
- DECR_AND_LOAD(19);
+ decr_and_load(ctx, 19, t0);
/* Fall through */
case 1:
- DECR_AND_LOAD(18);
+ decr_and_load(ctx, 18, t0);
}
if (do_s1) {
- DECR_AND_LOAD(17);
+ decr_and_load(ctx, 17, t0);
}
if (do_s0) {
- DECR_AND_LOAD(16);
+ decr_and_load(ctx, 16, t0);
}
switch (aregs) {
@@ -374,18 +380,17 @@ static void gen_mips16_restore(DisasContext *ctx,
}
if (astatic > 0) {
- DECR_AND_LOAD(7);
+ decr_and_load(ctx, 7, t0);
if (astatic > 1) {
- DECR_AND_LOAD(6);
+ decr_and_load(ctx, 6, t0);
if (astatic > 2) {
- DECR_AND_LOAD(5);
+ decr_and_load(ctx, 5, t0);
if (astatic > 3) {
- DECR_AND_LOAD(4);
+ decr_and_load(ctx, 4, t0);
}
}
}
}
-#undef DECR_AND_LOAD
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions
2024-09-30 9:10 ` [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
@ 2024-10-03 22:55 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-10-03 22:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
> Functions are easier to rework than macros. Besides,
> there is no gain here in inlining these.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/mips16e_translate.c.inc | 101 +++++++++++++-----------
> 1 file changed, 53 insertions(+), 48 deletions(-)
>
> diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
> index 5cffe0e412..31bc14f9ca 100644
> --- a/target/mips/tcg/mips16e_translate.c.inc
> +++ b/target/mips/tcg/mips16e_translate.c.inc
> @@ -122,11 +122,23 @@ enum {
>
> static int xlat(int r)
> {
> - static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
> + static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
>
> return map[r];
> }
>
> +static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
> +{
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + tcg_gen_movi_tl(t2, -4);
> + gen_op_addr_add(ctx, t0, t0, t2);
Code movement, so:
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
However, for cleanup, pass tcg_constant_tl(-4) instead of moving -4 into t2.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 05/12] target/mips: Introduce mo_endian() helper
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 04/12] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-10-03 22:56 ` Richard Henderson
2024-09-30 9:10 ` [PATCH 06/12] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
` (7 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Introduce mo_endian() which returns the endian MemOp
corresponding to the vCPU DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 2b6646b339..54955437ef 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -240,4 +240,9 @@ static inline bool cpu_is_bigendian(DisasContext *ctx)
return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
}
+static inline MemOp mo_endian(DisasContext *dc)
+{
+ return cpu_is_bigendian(dc) ? MO_BE : MO_LE;
+}
+
#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 05/12] target/mips: Introduce mo_endian() helper
2024-09-30 9:10 ` [PATCH 05/12] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
@ 2024-10-03 22:56 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-10-03 22:56 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
> Introduce mo_endian() which returns the endian MemOp
> corresponding to the vCPU DisasContext.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/translate.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
> index 2b6646b339..54955437ef 100644
> --- a/target/mips/tcg/translate.h
> +++ b/target/mips/tcg/translate.h
> @@ -240,4 +240,9 @@ static inline bool cpu_is_bigendian(DisasContext *ctx)
> return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
> }
>
> +static inline MemOp mo_endian(DisasContext *dc)
> +{
> + return cpu_is_bigendian(dc) ? MO_BE : MO_LE;
> +}
Based on patch 6, I think you'd better pass 'bool reversed' to this function.
Then
disas_is_bigendian(dc) ^ reversed ? MO_BE : MO_LE;
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 06/12] target/mips: Explode MO_TExx -> MO_TE | MO_xx
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 05/12] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-10-01 9:56 ` Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 07/12] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
` (6 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/mips); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/mxu_translate.c | 8 +-
target/mips/tcg/translate.c | 120 +++++++++++-----------
target/mips/tcg/tx79_translate.c | 8 +-
target/mips/tcg/micromips_translate.c.inc | 22 ++--
target/mips/tcg/mips16e_translate.c.inc | 12 +--
target/mips/tcg/nanomips_translate.c.inc | 32 +++---
6 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index c517258ac5..b221f7a4a0 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
@@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
gen_load_mxu_gpr(t1, XRa);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
if (postinc) {
@@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
@@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
gen_load_mxu_gpr(t1, XRa);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
if (postinc) {
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 333469b268..906fd3d73c 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
-OP_LD_ATOMIC(ll, MO_TESL);
+OP_LD_ATOMIC(ll, MO_TE | MO_SL);
#if defined(TARGET_MIPS64)
-OP_LD_ATOMIC(lld, MO_TEUQ);
+OP_LD_ATOMIC(lld, MO_TE | MO_UQ);
#endif
#undef OP_LD_ATOMIC
@@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LD:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LDL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL);
gen_store_gpr(t0, rt);
break;
case OPC_LWE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LW:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LH:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LHU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL);
+ gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_SDL:
@@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SW:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
case OPC_SHE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SH:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_SBE:
@@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
case OPC_LWC1:
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, ft);
}
@@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, ft);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
}
break;
case OPC_LDC1:
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft);
}
@@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
}
break;
@@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
case R6_OPC_LWPC:
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL);
break;
#if defined(TARGET_MIPS64)
case OPC_LWUPC:
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL);
break;
#endif
default:
@@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 3, 0, 21);
addr = addr_add(ctx, (pc & ~0x7), offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ);
+ gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ);
break;
#endif
default:
@@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLQ:
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rt);
gen_store_gpr(t0, lsq_rt1);
@@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t1, rt);
gen_store_fpr64(ctx, t0, lsq_rt1);
@@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_gpr(t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSQC1:
@@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_fpr64(ctx, t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
case OPC_GSLDRC1:
@@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
#endif
@@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_store_gpr(t0, rt);
break;
case OPC_GSLHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t0, rt);
break;
@@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
case OPC_GSSHX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSWX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
case OPC_GSSWXC1:
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDXC1:
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fd);
}
@@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
check_cp1_registers(ctx, fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL);
}
break;
case OPC_SDXC1:
@@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
}
break;
case OPC_SUXC1:
@@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
}
break;
}
@@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0);
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL);
gen_store_gpr(t1, rd);
}
@@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, rd);
break;
case OPC_LHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW);
gen_store_gpr(t0, rd);
break;
case OPC_LWX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
gen_store_gpr(t0, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_LDX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t0, rd);
break;
#endif
@@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
break;
case R6_OPC_SC:
- gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
break;
case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm);
@@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#endif
#if defined(TARGET_MIPS64)
case R6_OPC_SCD:
- gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
break;
case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm);
@@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SCE:
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true);
return;
case OPC_CACHEE:
check_eva(ctx);
@@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
break;
case OPC_CACHE:
check_cp0_enabled(ctx);
@@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS_R6) {
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index dd6fb8a7bd..1d290b86a9 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t0, a->rt);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_gpr_hi(t0, a->rt);
return true;
}
@@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
/* Lower half */
gen_load_gpr(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
return true;
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 7510831701..343d64a0e8 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SWP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
#ifdef TARGET_MIPS64
@@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SDP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, mips32_op, rt, rs, offset);
break;
case SC:
- gen_st_cond(ctx, rt, rs, offset, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false);
+ gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false);
break;
#endif
case LD_EVA:
@@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SHE;
goto do_st_lr;
case SCE:
- gen_st_cond(ctx, rt, rs, offset, MO_TESL, true);
+ gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true);
break;
case SWE:
mips32_op = OPC_SWE;
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 31bc14f9ca..9dd867fe89 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
gen_load_gpr(t1, regidx);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx,
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, regidx);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index b4b746d418..40ef0346a7 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN);
+ tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN);
if (cpu_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {
@@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
gen_base_offset_addr(ctx, va, 29, this_offset);
gen_load_gpr(t0, this_rt);
tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
- (MO_TEUL | ctx->default_tcg_memop_mask));
+ (MO_TE | MO_UL | ctx->default_tcg_memop_mask));
counter++;
}
@@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
int this_offset = u - ((counter + 1) << 2);
gen_base_offset_addr(ctx, va, 29, this_offset);
- tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, this_rt);
@@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHX:
/*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TESW | ctx->default_tcg_memop_mask);
+ MO_TE | MO_SW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LWX:
/*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TESL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_SL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LBUX:
@@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHUX:
/*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TEUW | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_SBX:
@@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUW | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UW | ctx->default_tcg_memop_mask);
break;
case NM_SWX:
/*case NM_SWXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UL | ctx->default_tcg_memop_mask);
break;
case NM_LWC1X:
/*case NM_LWC1XS:*/
@@ -3737,7 +3737,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
- MO_TESL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_SL | ctx->default_tcg_memop_mask);
}
break;
case NM_SWPC48:
@@ -3754,7 +3754,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UL | ctx->default_tcg_memop_mask);
}
break;
default:
@@ -4132,13 +4132,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 4)) {
case NM_UALH:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
MO_UNALN);
gen_store_gpr(t0, rt);
break;
case NM_UASH:
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
MO_UNALN);
break;
}
@@ -4161,7 +4161,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_SC:
switch (ctx->opcode & 0x03) {
case NM_SC:
- gen_st_cond(ctx, rt, rs, s, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false);
break;
case NM_SCWP:
check_xnp(ctx);
@@ -4274,7 +4274,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, s, MO_TESL, true);
+ gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true);
break;
case NM_SCWPE:
check_xnp(ctx);
@@ -4317,7 +4317,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 1)) {
case NM_LWM:
tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
- memop | MO_TESL);
+ memop | MO_TE | MO_SL);
gen_store_gpr(t1, this_rt);
if ((this_rt == rs) &&
(counter != (count - 1))) {
@@ -4328,7 +4328,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
this_rt = (rt == 0) ? 0 : this_rt;
gen_load_gpr(t1, this_rt);
tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
- memop | MO_TEUL);
+ memop | MO_TE | MO_UL);
break;
}
counter++;
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 06/12] target/mips: Explode MO_TExx -> MO_TE | MO_xx
2024-09-30 9:10 ` [PATCH 06/12] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
@ 2024-10-01 9:56 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-01 9:56 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Richard Henderson, Jiaxun Yang, Aleksandar Rikalo, Huacai Chen,
Anton Johansson
On Mon, Sep 30, 2024 at 11:12 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Extract the implicit MO_TE definition in order to replace
> it by runtime variable in the next commit.
>
> Mechanical change using:
>
> $ for n in UW UL UQ UO SW SL SQ; do \
> sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
> $(git grep -l MO_TE$n target/mips); \
> done
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/mxu_translate.c | 8 +-
> target/mips/tcg/translate.c | 120 +++++++++++-----------
> target/mips/tcg/tx79_translate.c | 8 +-
> target/mips/tcg/micromips_translate.c.inc | 22 ++--
> target/mips/tcg/mips16e_translate.c.inc | 12 +--
> target/mips/tcg/nanomips_translate.c.inc | 32 +++---
> 6 files changed, 101 insertions(+), 101 deletions(-)
>
> diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
> index c517258ac5..b221f7a4a0 100644
> --- a/target/mips/tcg/mxu_translate.c
> +++ b/target/mips/tcg/mxu_translate.c
> @@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
> tcg_gen_add_tl(t0, t0, t1);
>
> tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
> - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
> + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
Hmm either I need to use parenthesis here or swap the arguments.
> ctx->default_tcg_memop_mask);
> gen_store_mxu_gpr(t1, XRa);
>
> @@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
>
> gen_load_mxu_gpr(t1, XRa);
> tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
> - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
> + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
> ctx->default_tcg_memop_mask);
>
> if (postinc) {
> @@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
> tcg_gen_add_tl(t0, t0, t1);
>
> tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
> - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
> + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
> ctx->default_tcg_memop_mask);
> gen_store_mxu_gpr(t1, XRa);
>
> @@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
>
> gen_load_mxu_gpr(t1, XRa);
> tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
> - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
> + (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
> ctx->default_tcg_memop_mask);
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 07/12] target/mips: Replace MO_TE by mo_endian()
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 06/12] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
` (5 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.
Mechanical change using:
$ sed -i -e 's/MO_TE/mo_endian(ctx)/' \
$(git grep -l MO_TE target/mips)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/msa_helper.c | 2 +-
target/mips/tcg/mxu_translate.c | 18 ++--
target/mips/tcg/translate.c | 120 +++++++++++-----------
target/mips/tcg/tx79_translate.c | 8 +-
target/mips/tcg/micromips_translate.c.inc | 22 ++--
target/mips/tcg/mips16e_translate.c.inc | 12 +--
target/mips/tcg/nanomips_translate.c.inc | 32 +++---
7 files changed, 107 insertions(+), 107 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index d2181763e7..0d517b8062 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#if !defined(CONFIG_USER_ONLY)
#define MEMOP_IDX(DF) \
- MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
+ MemOpIdx oi = make_memop_idx(mo_endian(dc) | DF | MO_UNALN, \
mips_env_mmu_index(env));
#else
#define MEMOP_IDX(DF)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index b221f7a4a0..f25fb8eda8 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
- (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
+ ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
@@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
gen_load_mxu_gpr(t1, XRa);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
+ ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
if (postinc) {
@@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
- (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
+ ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
@@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
gen_load_mxu_gpr(t1, XRa);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- (MO_TE | MO_SL ^ (reversed ? MO_BSWAP : 0)) |
+ ((mo_endian(ctx) | MO_SL) ^ (reversed ? MO_BSWAP : 0)) |
ctx->default_tcg_memop_mask);
if (postinc) {
@@ -4803,19 +4803,19 @@ static void decode_opc_mxu__pool17(DisasContext *ctx)
switch (opcode) {
case OPC_MXU_LXW:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_UL);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UL);
break;
case OPC_MXU_LXB:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_SB);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SB);
break;
case OPC_MXU_LXH:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_SW);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SW);
break;
case OPC_MXU_LXBU:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_UB);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UB);
break;
case OPC_MXU_LXHU:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_UW);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UW);
break;
default:
MIPS_INVAL("decode_opc_mxu");
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 906fd3d73c..f2f974bfcd 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
-OP_LD_ATOMIC(ll, MO_TE | MO_SL);
+OP_LD_ATOMIC(ll, mo_endian(dc) | MO_SL);
#if defined(TARGET_MIPS64)
-OP_LD_ATOMIC(lld, MO_TE | MO_UQ);
+OP_LD_ATOMIC(lld, mo_endian(dc) | MO_UQ);
#endif
#undef OP_LD_ATOMIC
@@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LD:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LDL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
+ gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
+ gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rt);
break;
case OPC_LWE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LW:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LH:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LHU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
+ gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
+ gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_SDL:
@@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SW:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
case OPC_SHE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SH:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_SBE:
@@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
case OPC_LWC1:
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, ft);
}
@@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, ft);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
}
break;
case OPC_LDC1:
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft);
}
@@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
}
break;
@@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
case R6_OPC_LWPC:
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL);
break;
#if defined(TARGET_MIPS64)
case OPC_LWUPC:
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL);
break;
#endif
default:
@@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 3, 0, 21);
addr = addr_add(ctx, (pc & ~0x7), offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ);
+ gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
break;
#endif
default:
@@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLQ:
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rt);
gen_store_gpr(t0, lsq_rt1);
@@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t1, rt);
gen_store_fpr64(ctx, t0, lsq_rt1);
@@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_gpr(t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSQC1:
@@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_fpr64(ctx, t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
case OPC_GSLDRC1:
@@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
#endif
@@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_store_gpr(t0, rt);
break;
case OPC_GSLHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t0, rt);
break;
@@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
case OPC_GSSHX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSWX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
case OPC_GSSWXC1:
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDXC1:
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fd);
}
@@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
check_cp1_registers(ctx, fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
}
break;
case OPC_SDXC1:
@@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
}
break;
case OPC_SUXC1:
@@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
}
break;
}
@@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0);
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t1, rd);
}
@@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, rd);
break;
case OPC_LHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
gen_store_gpr(t0, rd);
break;
case OPC_LWX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_LDX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rd);
break;
#endif
@@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
break;
case R6_OPC_SC:
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
break;
case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm);
@@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#endif
#if defined(TARGET_MIPS64)
case R6_OPC_SCD:
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
break;
case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm);
@@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SCE:
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true);
return;
case OPC_CACHEE:
check_eva(ctx);
@@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
break;
case OPC_CACHE:
check_cp0_enabled(ctx);
@@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS_R6) {
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 1d290b86a9..ae3f5e19c4 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, a->rt);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr_hi(t0, a->rt);
return true;
}
@@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
/* Lower half */
gen_load_gpr(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
return true;
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 343d64a0e8..171508f7de 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SWP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
#ifdef TARGET_MIPS64
@@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SDP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, mips32_op, rt, rs, offset);
break;
case SC:
- gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, false);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false);
+ gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_UQ, false);
break;
#endif
case LD_EVA:
@@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SHE;
goto do_st_lr;
case SCE:
- gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true);
+ gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, true);
break;
case SWE:
mips32_op = OPC_SWE;
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 9dd867fe89..3943bf3368 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
gen_load_gpr(t1, regidx);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx,
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, regidx);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 40ef0346a7..65e6e759e4 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN);
+ tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, mo_endian(ctx) | MO_UQ | MO_ALIGN);
if (cpu_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {
@@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
gen_base_offset_addr(ctx, va, 29, this_offset);
gen_load_gpr(t0, this_rt);
tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
- (MO_TE | MO_UL | ctx->default_tcg_memop_mask));
+ (mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask));
counter++;
}
@@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
int this_offset = u - ((counter + 1) << 2);
gen_base_offset_addr(ctx, va, 29, this_offset);
- tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, this_rt);
@@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHX:
/*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TE | MO_SW | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LWX:
/*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TE | MO_SL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LBUX:
@@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHUX:
/*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TE | MO_UW | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_SBX:
@@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TE | MO_UW | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask);
break;
case NM_SWX:
/*case NM_SWXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TE | MO_UL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
break;
case NM_LWC1X:
/*case NM_LWC1XS:*/
@@ -3737,7 +3737,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
- MO_TE | MO_SL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
}
break;
case NM_SWPC48:
@@ -3754,7 +3754,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TE | MO_UL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
}
break;
default:
@@ -4132,13 +4132,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 4)) {
case NM_UALH:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW |
MO_UNALN);
gen_store_gpr(t0, rt);
break;
case NM_UASH:
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW |
MO_UNALN);
break;
}
@@ -4161,7 +4161,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_SC:
switch (ctx->opcode & 0x03) {
case NM_SC:
- gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL, false);
break;
case NM_SCWP:
check_xnp(ctx);
@@ -4274,7 +4274,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true);
+ gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL, true);
break;
case NM_SCWPE:
check_xnp(ctx);
@@ -4317,7 +4317,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 1)) {
case NM_LWM:
tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
- memop | MO_TE | MO_SL);
+ memop | mo_endian(ctx) | MO_SL);
gen_store_gpr(t1, this_rt);
if ((this_rt == rs) &&
(counter != (count - 1))) {
@@ -4328,7 +4328,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
this_rt = (rt == 0) ? 0 : this_rt;
gen_load_gpr(t1, this_rt);
tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
- memop | MO_TE | MO_UL);
+ memop | mo_endian(ctx) | MO_UL);
break;
}
counter++;
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 07/12] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-10-03 22:59 ` Richard Henderson
2024-09-30 9:10 ` [PATCH 09/12] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
` (4 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.h | 3 +++
target/mips/cpu.c | 9 ++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3e906a175a..070e11fe0d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1209,6 +1209,9 @@ struct ArchCPU {
Clock *clock;
Clock *count_div; /* Divider for CP0_Count clock */
+
+ /* Properties */
+ bool is_big_endian;
};
/**
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 89655b1900..982f5bb4e2 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
- env->CP0_Config0 = env->cpu_model->CP0_Config0;
+ env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
+ CP0C0_BE, 1, cpu->is_big_endian);
#if TARGET_BIG_ENDIAN
env->CP0_Config0 |= (1 << CP0C0_BE);
#endif
@@ -541,6 +542,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
};
#endif
+static Property mips_cpu_properties[] = {
+ DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -571,6 +577,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
+ device_class_set_props(dc, mips_cpu_properties);
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property
2024-09-30 9:10 ` [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
@ 2024-10-03 22:59 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-10-03 22:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
> Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/cpu.h | 3 +++
> target/mips/cpu.c | 9 ++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 3e906a175a..070e11fe0d 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1209,6 +1209,9 @@ struct ArchCPU {
>
> Clock *clock;
> Clock *count_div; /* Divider for CP0_Count clock */
> +
> + /* Properties */
> + bool is_big_endian;
> };
>
> /**
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 89655b1900..982f5bb4e2 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
>
> /* Reset registers to their default values */
> env->CP0_PRid = env->cpu_model->CP0_PRid;
> - env->CP0_Config0 = env->cpu_model->CP0_Config0;
> + env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
> + CP0C0_BE, 1, cpu->is_big_endian);
> #if TARGET_BIG_ENDIAN
> env->CP0_Config0 |= (1 << CP0C0_BE);
> #endif
Missed removing this ifdef.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 09/12] hw/mips/cps: Set the vCPU 'cpu-big-endian' property
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-09-30 9:10 ` [PATCH 10/12] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
` (3 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Have the CPS expose a 'cpu-big-endian' property so it can
set it to the vCPUs it creates.
Note, since the number of vCPUs created is dynamic, we can
not use QOM aliases.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/mips/cps.h | 1 +
hw/mips/cps.c | 4 ++++
hw/mips/malta.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 04d636246a..05ef9f76b7 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -38,6 +38,7 @@ struct MIPSCPSState {
uint32_t num_vp;
uint32_t num_irq;
char *cpu_type;
+ bool cpu_is_bigendian;
MemoryRegion container;
MIPSGCRState gcr;
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 07b73b0a1f..13046628cd 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -77,6 +77,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
CPUMIPSState *env = &cpu->env;
+ object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bigendian,
+ &error_abort);
+
/* All VPs are halted on reset. Leave powering up to CPC. */
object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
&error_abort);
@@ -167,6 +170,7 @@ static Property mips_cps_properties[] = {
DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
+ DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 6e73c896ff..a0757f251a 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1055,6 +1055,8 @@ static void create_cps(MachineState *ms, MaltaState *s,
object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
&error_fatal);
+ object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian",
+ TARGET_BIG_ENDIAN, &error_abort);
object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
&error_fatal);
qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 10/12] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 09/12] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
@ 2024-09-30 9:10 ` Philippe Mathieu-Daudé
2024-09-30 9:11 ` [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold() Philippe Mathieu-Daudé
` (2 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:10 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU
endianness requested by argument. Update the board call sites.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.h | 4 +++-
hw/mips/fuloong2e.c | 2 +-
hw/mips/jazz.c | 2 +-
hw/mips/loongson3_virt.c | 2 +-
hw/mips/malta.c | 3 ++-
hw/mips/mipssim.c | 2 +-
target/mips/cpu.c | 5 ++++-
7 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 070e11fe0d..a4a46ebbe9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1376,12 +1376,14 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
* mips_cpu_create_with_clock:
* @typename: a MIPS CPU type.
* @cpu_refclk: this cpu input clock (an output clock of another device)
+ * @is_big_endian: whether this CPU is configured in big endianness
*
* Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
* then realizes the CPU.
*
* Returns: A #CPUState or %NULL if an error occurred.
*/
-MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk);
+MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk,
+ bool is_big_endian);
#endif /* MIPS_CPU_H */
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 4fe5108845..50a3f06723 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -230,7 +230,7 @@ static void mips_fuloong2e_init(MachineState *machine)
clock_set_hz(cpuclk, 533080000); /* ~533 MHz */
/* init CPUs */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 0d44e19707..812e8cbcab 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -212,7 +212,7 @@ static void mips_jazz_init(MachineState *machine,
* ext_clk[jazz_model].pll_mult);
/* init CPUs */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, TARGET_BIG_ENDIAN);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 2067b4fecb..25fa94ee68 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -567,7 +567,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
int ip;
/* init CPUs */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index a0757f251a..71cc11fc45 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1035,7 +1035,8 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
int i;
for (i = 0; i < ms->smp.cpus; i++) {
- cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
+ cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
+ TARGET_BIG_ENDIAN);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index 9170d6c474..80b4a2c00d 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -160,7 +160,7 @@ mips_mipssim_init(MachineState *machine)
#endif
/* Init CPUs. */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, TARGET_BIG_ENDIAN);
env = &cpu->env;
reset_info = g_new0(ResetData, 1);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 982f5bb4e2..02e2e72f2d 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -646,12 +646,15 @@ static void mips_cpu_register_types(void)
type_init(mips_cpu_register_types)
/* Could be used by generic CPU object */
-MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
+MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk,
+ bool is_big_endian)
{
DeviceState *cpu;
cpu = DEVICE(object_new(cpu_type));
qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
+ object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian,
+ &error_abort);
qdev_realize(cpu, NULL, &error_abort);
return MIPS_CPU(cpu);
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold()
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2024-09-30 9:10 ` [PATCH 10/12] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
@ 2024-09-30 9:11 ` Philippe Mathieu-Daudé
2024-10-03 23:01 ` Richard Henderson
2024-09-30 9:11 ` [PATCH 12/12] hw/mips/malta: Remove TARGET_BIG_ENDIAN #ifdef'ry Philippe Mathieu-Daudé
2024-09-30 12:25 ` [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Jiaxun Yang
12 siblings, 1 reply; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:11 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Since all code creating vCPUs now set the 'cpu-big-endian' property,
we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold():
the CP0C0_BE bit is set using the property cpu->is_big_endian value.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 02e2e72f2d..9724e71a5e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -202,9 +202,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
env->CP0_PRid = env->cpu_model->CP0_PRid;
env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
CP0C0_BE, 1, cpu->is_big_endian);
-#if TARGET_BIG_ENDIAN
- env->CP0_Config0 |= (1 << CP0C0_BE);
-#endif
env->CP0_Config1 = env->cpu_model->CP0_Config1;
env->CP0_Config2 = env->cpu_model->CP0_Config2;
env->CP0_Config3 = env->cpu_model->CP0_Config3;
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold()
2024-09-30 9:11 ` [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold() Philippe Mathieu-Daudé
@ 2024-10-03 23:01 ` Richard Henderson
2024-10-10 20:22 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2024-10-03 23:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
On 9/30/24 02:11, Philippe Mathieu-Daudé wrote:
> Since all code creating vCPUs now set the 'cpu-big-endian' property,
> we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold():
> the CP0C0_BE bit is set using the property cpu->is_big_endian value.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/cpu.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 02e2e72f2d..9724e71a5e 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -202,9 +202,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
> env->CP0_PRid = env->cpu_model->CP0_PRid;
> env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
> CP0C0_BE, 1, cpu->is_big_endian);
> -#if TARGET_BIG_ENDIAN
> - env->CP0_Config0 |= (1 << CP0C0_BE);
> -#endif
> env->CP0_Config1 = env->cpu_model->CP0_Config1;
> env->CP0_Config2 = env->cpu_model->CP0_Config2;
> env->CP0_Config3 = env->cpu_model->CP0_Config3;
I think this must be merged into patch 8, or patch 8 doesn't work.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold()
2024-10-03 23:01 ` Richard Henderson
@ 2024-10-10 20:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 20:22 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
On 3/10/24 20:01, Richard Henderson wrote:
> On 9/30/24 02:11, Philippe Mathieu-Daudé wrote:
>> Since all code creating vCPUs now set the 'cpu-big-endian' property,
>> we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold():
>> the CP0C0_BE bit is set using the property cpu->is_big_endian value.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/mips/cpu.c | 3 ---
>> 1 file changed, 3 deletions(-)
>>
>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
>> index 02e2e72f2d..9724e71a5e 100644
>> --- a/target/mips/cpu.c
>> +++ b/target/mips/cpu.c
>> @@ -202,9 +202,6 @@ static void mips_cpu_reset_hold(Object *obj,
>> ResetType type)
>> env->CP0_PRid = env->cpu_model->CP0_PRid;
>> env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
>> CP0C0_BE, 1, cpu->is_big_endian);
>> -#if TARGET_BIG_ENDIAN
>> - env->CP0_Config0 |= (1 << CP0C0_BE);
>> -#endif
>> env->CP0_Config1 = env->cpu_model->CP0_Config1;
>> env->CP0_Config2 = env->cpu_model->CP0_Config2;
>> env->CP0_Config3 = env->cpu_model->CP0_Config3;
>
> I think this must be merged into patch 8, or patch 8 doesn't work.
Correct.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 12/12] hw/mips/malta: Remove TARGET_BIG_ENDIAN #ifdef'ry
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2024-09-30 9:11 ` [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold() Philippe Mathieu-Daudé
@ 2024-09-30 9:11 ` Philippe Mathieu-Daudé
2024-09-30 12:25 ` [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Jiaxun Yang
12 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-09-30 9:11 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Philippe Mathieu-Daudé, Richard Henderson, Jiaxun Yang,
Aleksandar Rikalo, Huacai Chen, Anton Johansson
Move code evaluation from preprocessor to compiler so
the if() ladder is always processed. Mostly to unify
style in not using TARGET_BIG_ENDIAN #ifdef anymore.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/malta.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 71cc11fc45..a3b6f63089 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1196,8 +1196,7 @@ void mips_malta_init(MachineState *machine)
* In little endian mode the 32bit words in the bios are swapped,
* a neat trick which allows bi-endian firmware.
*/
-#if !TARGET_BIG_ENDIAN
- {
+ if (!TARGET_BIG_ENDIAN) {
uint32_t *end, *addr;
const size_t swapsize = MIN(bios_size, 0x3e0000);
addr = rom_ptr(FLASH_ADDRESS, swapsize);
@@ -1210,7 +1209,6 @@ void mips_malta_init(MachineState *machine)
addr++;
}
}
-#endif
}
/*
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 00/12] target/mips: Remove target-specific endianness knowledge
2024-09-30 9:10 [PATCH 00/12] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2024-09-30 9:11 ` [PATCH 12/12] hw/mips/malta: Remove TARGET_BIG_ENDIAN #ifdef'ry Philippe Mathieu-Daudé
@ 2024-09-30 12:25 ` Jiaxun Yang
12 siblings, 0 replies; 21+ messages in thread
From: Jiaxun Yang @ 2024-09-30 12:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, QEMU devel
Cc: Thomas Huth, Aurelien Jarno, Hervé Poussineau,
Richard Henderson, Aleksandar Rikalo, Huacai Chen,
Anton Johansson
在2024年9月30日九月 上午10:10，Philippe Mathieu-Daudé写道：
> Get vCPU endianness from CP0::BE bit.
> Propagate endianness at the board level, using QOM property.
> Remove target-specific endianness knowledge from target/.
For the series:
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Will this lead us to bi-endian QEMU executable?
Thanks
- Jiaxun
>
> Philippe Mathieu-Daudé (12):
> target/mips: Declare cpu_is_bigendian_env() in 'internal.h'
> target/mips: Introduce mo_endian_env() helper
> target/mips: Replace MO_TE by mo_endian_env() in get_pte()
> target/mips: Convert mips16e decr_and_load/store() macros to functions
> target/mips: Introduce mo_endian() helper
> target/mips: Explode MO_TExx -> MO_TE | MO_xx
> target/mips: Replace MO_TE by mo_endian()
> target/mips: Expose MIPSCPU::is_big_endian property
> hw/mips/cps: Set the vCPU 'cpu-big-endian' property
> hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
> target/mips: Remove target-specific code in mips_cpu_reset_hold()
> hw/mips/malta: Remove TARGET_BIG_ENDIAN #ifdef'ry
>
> include/hw/mips/cps.h | 1 +
> target/mips/cpu.h | 7 +-
> target/mips/internal.h | 11 ++
> target/mips/tcg/translate.h | 5 +
> hw/mips/cps.c | 4 +
> hw/mips/fuloong2e.c | 2 +-
> hw/mips/jazz.c | 2 +-
> hw/mips/loongson3_virt.c | 2 +-
> hw/mips/malta.c | 9 +-
> hw/mips/mipssim.c | 2 +-
> target/mips/cpu.c | 17 ++-
> target/mips/tcg/ldst_helper.c | 15 +--
> target/mips/tcg/msa_helper.c | 2 +-
> target/mips/tcg/mxu_translate.c | 18 ++--
> target/mips/tcg/sysemu/tlb_helper.c | 2 +-
> target/mips/tcg/translate.c | 120 +++++++++++-----------
> target/mips/tcg/tx79_translate.c | 8 +-
> target/mips/tcg/micromips_translate.c.inc | 22 ++--
> target/mips/tcg/mips16e_translate.c.inc | 109 ++++++++++----------
> target/mips/tcg/nanomips_translate.c.inc | 32 +++---
> 20 files changed, 212 insertions(+), 178 deletions(-)
>
> --
> 2.45.2
--
- Jiaxun
^ permalink raw reply [flat|nested] 21+ messages in thread